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Python for System Verilog testbench

On 9/14/18 11:41 AM, Bobby wrote:
> Hi George
> WOW!  thanks for the reply and specially thanks for using the word 'BDD'. I
> read the articles regarding BDD the whole day and understood the concepts.
> Now will get this Pytest test framework with pytest bdd plugin. I found out
> it follows this Gherkin syntax. Then I read about this Gherkin synatx. It
> also looks good specially for Verilog. Maybe the syntax I was following
> earlier is too complicated.
> Some more questions regarding this:
> - I read that there are other Python framweorks also
> for BDD like 'behave'. What do you suggest as a beginner is Pytest-bdd is
> easier or 'behave' ?
> - If I am able to successfully map the requirements in pytest-bdd following
> this Gherkins syntax, in the end what we get is Python code. To proceed
> further, will I have to use Python to Verilog parser for the final Verilog
> kind of structure?

Hi Bobby,
It's better to either bottom post, or inline your comments as the thread 
gets mangled in the archives.

There is MyHDL that may be of some use: <http://www.myhdl.org/>

"MyHDL turns Python into a hardware description and verification 
language, providing hardware engineers with the power of the Python 

It supports synthesis from the Python RTL Models:

- Dale

> On Friday, September 14, 2018, George Fischhof <george at fischhof.hu> wrote:
>> Bobby <italienisch1987 at gmail.com> ezt ?rta (id?pont: 2018. szept. 14., P
> 0:16):
>>> I have a very simple System Verilog (SV) adder as my DUT (device under
> test). I would like to  generate a test bench for this DUT based on the
> 'requirements'. I wrote its  (DUT) functions in simple text as
> 'requirements' while following a particular syntax. Now through  the help
> of grammar, I would like to give the requirement input to the grammar.
>>> Questions:
>>>   (1)     Considering my end goal, i.e. to generate some particular parts
> of
>>>           SV testbench from requirements, any good python parser
> available ?
>>>   (2)     If I use python parser, will any kind of python scripting will
> help me to generate the testbench in SV for my DUT ? My confusion at this
> point is that most of all the literature I am reading suggests linguistic
> techniques. Any non-linguistic technique ?
>>> --
>>> https://mail.python.org/mailman/listinfo/python-list
>> Hi,
>> Perhaps you should check articles about BDD,  and you can use PyTest test
> framework with pytest-bdd plugin
>> __george__