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Python for System Verilog testbench


Bobby <italienisch1987 at gmail.com> ezt ?rta (id?pont: 2018. szept. 14., P
0:16):

>
> I have a very simple System Verilog (SV) adder as my DUT (device under
> test). I would like to  generate a test bench for this DUT based on the
> 'requirements'. I wrote its  (DUT) functions in simple text as
> 'requirements' while following a particular syntax. Now through  the help
> of grammar, I would like to give the requirement input to the grammar.
>
> Questions:
>
>  (1)     Considering my end goal, i.e. to generate some particular parts
> of
>          SV testbench from requirements, any good python parser available
> ?
>
>  (2)     If I use python parser, will any kind of python scripting will
> help me to generate the testbench in SV for my DUT ? My confusion at this
> point is that most of all the literature I am reading suggests linguistic
> techniques. Any non-linguistic technique ?
>
>
> --
> https://mail.python.org/mailman/listinfo/python-list



Hi,

Perhaps you should check articles about BDD,  and you can use PyTest test
framework with pytest-bdd plugin

__george__

>
>