--- oprofile-0.9.2.orig/events/Makefile.am
+++ oprofile-0.9.2/events/Makefile.am
@@ -24,6 +24,7 @@
 	x86-64/hammer/events x86-64/hammer/unit_masks \
 	arm/xscale1/events arm/xscale1/unit_masks \
 	arm/xscale2/events arm/xscale2/unit_masks \
+	arm/arm11/events arm/arm11/unit_masks \
 	mips/20K/events mips/20K/unit_masks \
 	mips/24K/events mips/24K/unit_masks \
 	mips/25K/events mips/25K/unit_masks \
--- oprofile-0.9.2.orig/events/arm/arm11/unit_masks
+++ oprofile-0.9.2/events/arm/arm11/unit_masks
@@ -0,0 +1,4 @@
+# Arm11 possible unit masks
+#
+name:zero type:mandatory default:0x00
+	0x00 No unit mask
--- oprofile-0.9.2.orig/events/arm/arm11/events
+++ oprofile-0.9.2/events/arm/arm11/events
@@ -0,0 +1,21 @@
+# ARM11 events
+#
+event:0x00 counters:1,2 um:zero minimum:500 name:IFU_IFETCH_MISS : number of instruction fetch misses
+event:0x01 counters:1,2 um:zero minimum:500 name:CYCLES_IFU_MEM_STALL : cycles instruction fetch pipe is stalled
+event:0x02 counters:1,2 um:zero minimum:500 name:CYCLES_DATA_STALL : cycles stall occurs for due to data dependency
+event:0x03 counters:1,2 um:zero minimum:500 name:ITLB_MISS : number of Instruction MicroTLB misses
+event:0x04 counters:1,2 um:zero minimum:500 name:DTLB_MISS : number of Data MicroTLB misses
+event:0x05 counters:1,2 um:zero minimum:500 name:BR_INST_EXECUTED : branch instruction executed w/ or w/o program flow change
+event:0x06 counters:1,2 um:zero minimum:500 name:BR_INST_MISS_PRED : branch mispredicted
+event:0x07 counters:1,2 um:zero minimum:500 name:INSN_EXECUTED : instructions executed
+event:0x09 counters:1,2 um:zero minimum:500 name:DCACHE_ACCESS : data cache access, cacheable locations
+event:0x0a counters:1,2 um:zero minimum:500 name:DCACHE_ACCESS_ALL : data cache access, all locations
+event:0x0b counters:1,2 um:zero minimum:500 name:DCACHE_MISS : data cache miss
+event:0x0c counters:1,2 um:zero minimum:500 name:DCACHE_WB : data cache writeback, 1 event for every half cacheline
+event:0x0d counters:1,2 um:zero minimum:500 name:PC_CHANGE : number of times the program counter was changed without a mode switch
+event:0x0f counters:1,2 um:zero minimum:500 name:TLB_MISS : Main TLB miss
+event:0x10 counters:1,2 um:zero minimum:500 name:EXP_EXTERNAL : Explict external data access
+event:0x11 counters:1,2 um:zero minimum:500 name:LSU_STALL : cycles stalled because Load Store request queque is full
+event:0x12 counters:1,2 um:zero minimum:500 name:WRITE_DRAIN : Time swrite buffer was drained
+event:0xfe counters:0 um:zero minimum:500 name:CPU_CYCLES : clock cycles counter
+# 
--- oprofile-0.9.2.orig/utils/ophelp.c
+++ oprofile-0.9.2/utils/ophelp.c
@@ -404,13 +404,14 @@
 		printf("See Alpha Architecture Reference Manual\n"
 		       "ftp://ftp.compaq.com/pub/products/alphaCPUdocs/alpha_arch_ref.pdf\n");
 		break;
+	case CPU_ARM_ARM11:
+		printf("See ARM11 Technical Reference Manual\n");
+		break;
 	case CPU_ARM_XSCALE1:
 	case CPU_ARM_XSCALE2:
 		printf("See Intel XScale Core Developer's Manual\n"
 		       "Chapter 8 Performance Monitoring\n");
 		break;
-		break;
-
 	case CPU_PPC64_POWER4:
 	case CPU_PPC64_POWER5:
 	case CPU_PPC64_POWER5p:
--- oprofile-0.9.2.orig/libop/op_cpu_type.c
+++ oprofile-0.9.2/libop/op_cpu_type.c
@@ -64,6 +64,7 @@
 	{ "Core Solo / Duo", "i386/core", CPU_CORE, 2 },
 	{ "PowerPC G4", "ppc/7450",  CPU_PPC_7450, 6 },
  	{ "Core 2", "i386/core_2", CPU_CORE_2, 2 },
+	{ "ARM11 PMU", "arm/arm11", CPU_ARM_ARM11, 3 },
 };
  
 static size_t const nr_cpu_descrs = sizeof(cpu_descrs) / sizeof(struct cpu_descr);
--- oprofile-0.9.2.orig/libop/op_cpu_type.h
+++ oprofile-0.9.2/libop/op_cpu_type.h
@@ -60,6 +60,7 @@
 	CPU_CORE, /**< Core Solo / Duo series */
 	CPU_PPC_7450, /**< PowerPC G4 */
 	CPU_CORE_2, /**< Intel Core 2 */
+	CPU_ARM_ARM11, /**< ARM11 */
 	MAX_CPU_TYPE
 } op_cpu;