Project : madwifi
Revision : 2797
Author : mcgrof (Luis R. Rodriguez)
Date : 2007-10-29 21:13:46 +0100 (Mon, 29 Oct 2007)
Log Message :
commit b2fb1a4f75acf28c3296023651930acdb0989ffb
Author: Jiri Slaby <jirislaby@xxxxxxxxx>
Date: Fri Oct 19 18:57:13 2007 -0400
[PATCH] Net: ath5k, minor fixes
ath5k, minor fixes
- some -W compiler warnings fixes (signedness)
- make ath_stop static
- add BUG to ath5k_register_mode when passing supported but
not filled mode and move the supported modes check into
this function to simplify the macro
Signed-off-by: Jiri Slaby <jirislaby@xxxxxxxxx>
Signed-off-by: John W. Linville <linville@xxxxxxxxxxxxx>
commit 4d76a69bb9580208e984a593a3c53c04241ef95f
Author: John W. Linville <linville@xxxxxxxxxxxxx>
Date: Tue Oct 23 13:41:37 2007 -0400
[PATCH] ath5k: undo overzealous hunk of "ath5k: avoid oops when..."
The first hunk of "ath5k: avoid oops when ah_capabilities.cap_mode not
set" was ill-advised. It can cause its loop to abort prematurely.
Signed-off-by: John W. Linville <linville@xxxxxxxxxxxxx>
commit acce518756e5f4d2b346fde83fbdabf771c589e7
Author: Bruno Randolf <bruno@xxxxxxxxxxxxx>
Date: Fri Oct 19 23:57:27 2007 +0900
[PATCH] ath5k: mac revision fixes
this are two small fixes:
1) actually print the mac revision when we say so
2) better check for mac revisions when putting device to sleep: this is
important with newer mac revisions (>=7.8) which will freeze the
whole system when put to sleep
Signed-off-by: Bruno Randolf <bruno@xxxxxxxxxxxxx>
Signed-off-by: John W. Linville <linville@xxxxxxxxxxxxx>
commit 3d86396cd6d5b0f3c61a5c151aeb59d56afb390b
Author: Nick Kossifidis <mick@xxxxxxxxxxx>
Date: Fri Oct 19 13:56:19 2007 +0000
[PATCH] ath5k: Maintain naming scheme
Use "ath5k_" instead of "ath_" and "ah" instead of "hal"
Changes to base.c, base.h
Changes-licensed-under: 3-clause-BSD
Changes to ath5k.h, hw.c, hw.h, reg.h
Changes-licensed-under: ISC
Signed-Off-by: Nick Kossifidis <mickflemm@xxxxxxxxx>
Signed-off-by: John W. Linville <linville@xxxxxxxxxxxxx>
Affected Files:
* ath5k/trunk/ath5k.h updated
* ath5k/trunk/base.c updated
* ath5k/trunk/base.h updated
* ath5k/trunk/hw.c updated
* ath5k/trunk/hw.h updated
* ath5k/trunk/initvals.c updated
* ath5k/trunk/phy.c updated
* ath5k/trunk/reg.h updated
Modified: ath5k/trunk/ath5k.h
===================================================================
--- ath5k/trunk/ath5k.h 2007-10-29 05:07:38 UTC (rev 2796)
+++ ath5k/trunk/ath5k.h 2007-10-29 20:13:46 UTC (rev 2797)
@@ -26,7 +26,7 @@
#define CHAN_DEBUG 0
/* Uncomment this for debuging (warning that it results in TOO much output) */
-/*#define AR5K_DEBUG 1 */
+/* #define AR5K_DEBUG 1 */
#include <linux/io.h>
#include <linux/types.h>
@@ -206,6 +206,7 @@
* algorithm. This is done transparently. Once this feature is enabled,
* compression and decompression takes place inside the chipset, without
* putting additional load on the host CPU.
+ *
*/
#define MODULATION_TURBO 0x00000080
@@ -230,7 +231,7 @@
/*
* Tx Descriptor
*/
-struct ath_tx_status {
+struct ath5k_tx_status {
u16 ts_seqnum;
u16 ts_tstamp;
u8 ts_status;
@@ -277,7 +278,7 @@
};
/*
- * Queue ID numbers as returned by the HAL, each number
+ * Queue ID numbers as returned by the hw functions, each number
* represents a hw queue. If hw does not support hw queues
* (eg 5210) all data goes in one queue. These match
* d80211 definitions (net80211/MadWiFi don't use them).
@@ -297,6 +298,8 @@
/*
* Flags to set hw queue's parameters...
+ * TODO: Implement missing stuff (almost there,
+ * probably have to tweak with SISR).
*/
#define AR5K_TXQ_FLAG_TXINT_ENABLE 0x0001 /* Enable TXOK and
TXERR interrupts -not used- */
#define AR5K_TXQ_FLAG_TXDESCINT_ENABLE 0x0002 /* Enable TXDESC
interrupt -not implemented- */
@@ -321,7 +324,6 @@
u32 tqi_cbr_overflow_limit;
u32 tqi_burst_time;
u32 tqi_ready_time; /* Not used */
- u32 tqi_comp_buffer;/* Compression Buffer's phys addr */
};
/*
@@ -342,11 +344,11 @@
*/
#define AR5K_TXPOWER_OFDM(_r, _v) ( \
((0 & 1) << ((_v) + 6)) | \
- (((hal->ah_txpower.txp_rates[(_r)]) & 0x3f) << (_v)) \
+ (((ah->ah_txpower.txp_rates[(_r)]) & 0x3f) << (_v)) \
)
#define AR5K_TXPOWER_CCK(_r, _v) ( \
- (hal->ah_txpower.txp_rates[(_r)] & 0x3f) << (_v) \
+ (ah->ah_txpower.txp_rates[(_r)] & 0x3f) << (_v) \
)
/*
@@ -451,7 +453,7 @@
/*
* Rx Descriptor
*/
-struct ath_rx_status {
+struct ath5k_rx_status {
u16 rs_datalen;
u16 rs_tstamp;
u8 rs_status;
@@ -519,7 +521,7 @@
/*
* Atheros descriptor
*/
-struct ath_desc {
+struct ath5k_desc {
u32 ds_link;
u32 ds_data;
u32 ds_ctl0;
@@ -527,8 +529,8 @@
u32 ds_hw[4];
union {
- struct ath_rx_status rx;
- struct ath_tx_status tx;
+ struct ath5k_rx_status rx;
+ struct ath5k_tx_status tx;
} ds_us;
#define ds_rxstat ds_us.rx
@@ -593,6 +595,8 @@
/*
* Rate definitions
+ * TODO: Clean them up or move them on mac80211 -most of these infos are
+ * used by the rate control algorytm on MadWiFi.
*/
#define AR5K_MAX_RATES 32 /*max number of rates on the rate table*/
@@ -600,14 +604,15 @@
struct ath5k_rate {
u8 valid; /* Valid for rate control */
u32 modulation;
- u16 rate_kbps;
+ u16 rate_kbps; /* Rate in kbps used in computetxtime */
u8 rate_code; /* Rate mapping for h/w descriptors */
u8 dot11_rate;
- u8 control_rate;
- u16 lp_ack_duration;/* long preamble ACK duration */
- u16 sp_ack_duration;/* short preamble ACK duration*/
+ u8 control_rate; /* Rate for management frames -not used */
+ u16 lp_ack_duration;/* long preamble ACK duration -not used */
+ u16 sp_ack_duration;/* short preamble ACK duration -not used */
};
+/* XXX: GRR all this stuff to get leds blinking ??? (check out setcurmode) */
struct ath5k_rate_table {
u16 rate_count;
u8 rate_code_to_index[AR5K_MAX_RATES]; /* Back-mapping */
@@ -720,7 +725,7 @@
};
/*
- * HAL interrupt abstraction
+ * Hardware interrupt abstraction
*/
/**
@@ -734,7 +739,7 @@
* Queue Control Unit (QCU) signals an EOL interrupt only if a descriptor's
* LinkPtr is NULL. For more details, refer to:
* http://www.freepatentsonline.com/20030225739.html
- * @AR5K_INT_RXORN: indicates a hardware reset is required on certain hardware.
+ * @AR5K_INT_RXORN: Indicates we got RX overrun (eg. no more descriptors).
* Note that Rx overrun is not always fatal, on some chips we can continue
* operation without reseting the card, that's why int_fatal is not
* common for all chips.
@@ -836,7 +841,7 @@
#define AR5K_SOFTLED_OFF 1
/*
- * Chipset capabilities -see ath_hal_getcapability-
+ * Chipset capabilities -see ath5k_hw_get_capability-
* get_capability function is not yet fully implemented
* in OpenHAL so most of these don't work yet...
*/
@@ -913,7 +918,7 @@
#define AR5K_MAX_GPIO 10
#define AR5K_MAX_RF_BANKS 8
-struct ath_hw {
+struct ath5k_hw {
u32 ah_magic;
void *ah_sc;
@@ -997,17 +1002,17 @@
/*
* Function pointers
*/
- int (*ah_setup_tx_desc)(struct ath_hw *, struct ath_desc *,
+ int (*ah_setup_tx_desc)(struct ath5k_hw *, struct ath5k_desc *,
unsigned int, unsigned int, enum ath5k_pkt_type, unsigned int,
unsigned int, unsigned int, unsigned int, unsigned int,
unsigned int, unsigned int, unsigned int);
- bool (*ah_setup_xtx_desc)(struct ath_hw *, struct ath_desc *,
+ bool (*ah_setup_xtx_desc)(struct ath5k_hw *, struct ath5k_desc *,
unsigned int, unsigned int, unsigned int, unsigned int,
unsigned int, unsigned int);
- int (*ah_fill_tx_desc)(struct ath_hw *, struct ath_desc *,
+ int (*ah_fill_tx_desc)(struct ath5k_hw *, struct ath5k_desc *,
unsigned int, bool, bool);
- int (*ah_proc_tx_desc)(struct ath_hw *, struct ath_desc *);
- int (*ah_proc_rx_desc)(struct ath_hw *, struct ath_desc *);
+ int (*ah_proc_tx_desc)(struct ath5k_hw *, struct ath5k_desc *);
+ int (*ah_proc_rx_desc)(struct ath5k_hw *, struct ath5k_desc *);
};
/*
@@ -1015,123 +1020,123 @@
*/
/* General Functions */
-extern int ath5k_hw_register_timeout(struct ath_hw *hal, u32 reg, u32 flag,
u32 val, bool is_set);
+extern int ath5k_hw_register_timeout(struct ath5k_hw *ah, u32 reg, u32 flag,
u32 val, bool is_set);
/* Attach/Detach Functions */
-extern struct ath_hw *ath5k_hw_attach(u16 device, u8 mac_version, void *sc,
void __iomem *sh);
-extern const struct ath5k_rate_table *ath5k_hw_get_rate_table(struct ath_hw
*hal, unsigned int mode);
-extern void ath5k_hw_detach(struct ath_hw *hal);
+extern struct ath5k_hw *ath5k_hw_attach(u16 device, u8 mac_version, void *sc,
void __iomem *sh);
+extern const struct ath5k_rate_table *ath5k_hw_get_rate_table(struct ath5k_hw
*ah, unsigned int mode);
+extern void ath5k_hw_detach(struct ath5k_hw *ah);
/* Reset Functions */
-extern int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode,
struct ieee80211_channel *channel, bool change_channel);
+extern int ath5k_hw_reset(struct ath5k_hw *ah, enum ieee80211_if_types
op_mode, struct ieee80211_channel *channel, bool change_channel);
/* Power management functions */
-extern int ath5k_hw_set_power(struct ath_hw *hal, enum ath5k_power_mode mode,
bool set_chip, u16 sleep_duration);
+extern int ath5k_hw_set_power(struct ath5k_hw *ah, enum ath5k_power_mode mode,
bool set_chip, u16 sleep_duration);
/* DMA Related Functions */
-extern void ath5k_hw_start_rx(struct ath_hw *hal);
-extern int ath5k_hw_stop_rx_dma(struct ath_hw *hal);
-extern u32 ath5k_hw_get_rx_buf(struct ath_hw *hal);
-extern void ath5k_hw_put_rx_buf(struct ath_hw *hal, u32 phys_addr);
-extern int ath5k_hw_tx_start(struct ath_hw *hal, unsigned int queue);
-extern int ath5k_hw_stop_tx_dma(struct ath_hw *hal, unsigned int queue);
-extern u32 ath5k_hw_get_tx_buf(struct ath_hw *hal, unsigned int queue);
-extern int ath5k_hw_put_tx_buf(struct ath_hw *hal, unsigned int queue, u32
phys_addr);
-extern int ath5k_hw_update_tx_triglevel(struct ath_hw *hal, bool increase);
+extern void ath5k_hw_start_rx(struct ath5k_hw *ah);
+extern int ath5k_hw_stop_rx_dma(struct ath5k_hw *ah);
+extern u32 ath5k_hw_get_rx_buf(struct ath5k_hw *ah);
+extern void ath5k_hw_put_rx_buf(struct ath5k_hw *ah, u32 phys_addr);
+extern int ath5k_hw_tx_start(struct ath5k_hw *ah, unsigned int queue);
+extern int ath5k_hw_stop_tx_dma(struct ath5k_hw *ah, unsigned int queue);
+extern u32 ath5k_hw_get_tx_buf(struct ath5k_hw *ah, unsigned int queue);
+extern int ath5k_hw_put_tx_buf(struct ath5k_hw *ah, unsigned int queue, u32
phys_addr);
+extern int ath5k_hw_update_tx_triglevel(struct ath5k_hw *ah, bool increase);
/* Interrupt handling */
-extern bool ath5k_hw_is_intr_pending(struct ath_hw *hal);
-extern int ath5k_hw_get_isr(struct ath_hw *hal, enum ath5k_int
*interrupt_mask);
-extern enum ath5k_int ath5k_hw_set_intr(struct ath_hw *hal, enum ath5k_int
new_mask);
+extern bool ath5k_hw_is_intr_pending(struct ath5k_hw *ah);
+extern int ath5k_hw_get_isr(struct ath5k_hw *ah, enum ath5k_int
*interrupt_mask);
+extern enum ath5k_int ath5k_hw_set_intr(struct ath5k_hw *ah, enum ath5k_int
new_mask);
/* EEPROM access functions */
-extern int ath5k_hw_set_regdomain(struct ath_hw *hal, u16 regdomain);
+extern int ath5k_hw_set_regdomain(struct ath5k_hw *ah, u16 regdomain);
/* Protocol Control Unit Functions */
-extern int ath5k_hw_set_opmode(struct ath_hw *hal);
+extern int ath5k_hw_set_opmode(struct ath5k_hw *ah);
/* BSSID Functions */
-extern void ath5k_hw_get_lladdr(struct ath_hw *hal, u8 *mac);
-extern int ath5k_hw_set_lladdr(struct ath_hw *hal, const u8 *mac);
-extern void ath5k_hw_set_associd(struct ath_hw *hal, const u8 *bssid, u16
assoc_id);
-extern int ath5k_hw_set_bssid_mask(struct ath_hw *hal, const u8 *mask);
+extern void ath5k_hw_get_lladdr(struct ath5k_hw *ah, u8 *mac);
+extern int ath5k_hw_set_lladdr(struct ath5k_hw *ah, const u8 *mac);
+extern void ath5k_hw_set_associd(struct ath5k_hw *ah, const u8 *bssid, u16
assoc_id);
+extern int ath5k_hw_set_bssid_mask(struct ath5k_hw *ah, const u8 *mask);
/* Receive start/stop functions */
-extern void ath5k_hw_start_rx_pcu(struct ath_hw *hal);
-extern void ath5k_hw_stop_pcu_recv(struct ath_hw *hal);
+extern void ath5k_hw_start_rx_pcu(struct ath5k_hw *ah);
+extern void ath5k_hw_stop_pcu_recv(struct ath5k_hw *ah);
/* RX Filter functions */
-extern void ath5k_hw_set_mcast_filter(struct ath_hw *hal, u32 filter0, u32
filter1);
-extern int ath5k_hw_set_mcast_filterindex(struct ath_hw *hal, u32 index);
-extern int ath5k_hw_clear_mcast_filter_idx(struct ath_hw *hal, u32 index);
-extern u32 ath5k_hw_get_rx_filter(struct ath_hw *ah);
-extern void ath5k_hw_set_rx_filter(struct ath_hw *ah, u32 filter);
+extern void ath5k_hw_set_mcast_filter(struct ath5k_hw *ah, u32 filter0, u32
filter1);
+extern int ath5k_hw_set_mcast_filterindex(struct ath5k_hw *ah, u32 index);
+extern int ath5k_hw_clear_mcast_filter_idx(struct ath5k_hw *ah, u32 index);
+extern u32 ath5k_hw_get_rx_filter(struct ath5k_hw *ah);
+extern void ath5k_hw_set_rx_filter(struct ath5k_hw *ah, u32 filter);
/* Beacon related functions */
-extern u32 ath5k_hw_get_tsf32(struct ath_hw *hal);
-extern u64 ath5k_hw_get_tsf64(struct ath_hw *hal);
-extern void ath5k_hw_reset_tsf(struct ath_hw *hal);
-extern void ath5k_hw_init_beacon(struct ath_hw *hal, u32 next_beacon, u32
interval);
-extern int ath5k_hw_set_beacon_timers(struct ath_hw *hal, const struct
ath5k_beacon_state *state);
-extern void ath5k_hw_reset_beacon(struct ath_hw *hal);
-extern int ath5k_hw_wait_for_beacon(struct ath_hw *hal, unsigned long
phys_addr);
-extern void ath5k_hw_update_mib_counters(struct ath_hw *hal, struct
ath5k_mib_stats *statistics);
+extern u32 ath5k_hw_get_tsf32(struct ath5k_hw *ah);
+extern u64 ath5k_hw_get_tsf64(struct ath5k_hw *ah);
+extern void ath5k_hw_reset_tsf(struct ath5k_hw *ah);
+extern void ath5k_hw_init_beacon(struct ath5k_hw *ah, u32 next_beacon, u32
interval);
+extern int ath5k_hw_set_beacon_timers(struct ath5k_hw *ah, const struct
ath5k_beacon_state *state);
+extern void ath5k_hw_reset_beacon(struct ath5k_hw *ah);
+extern int ath5k_hw_wait_for_beacon(struct ath5k_hw *ah, unsigned long
phys_addr);
+extern void ath5k_hw_update_mib_counters(struct ath5k_hw *ah, struct
ath5k_mib_stats *statistics);
/* ACK/CTS Timeouts */
-extern int ath5k_hw_set_ack_timeout(struct ath_hw *hal, unsigned int timeout);
-extern unsigned int ath5k_hw_get_ack_timeout(struct ath_hw *hal);
-extern int ath5k_hw_set_cts_timeout(struct ath_hw *hal, unsigned int timeout);
-extern unsigned int ath5k_hw_get_cts_timeout(struct ath_hw *hal);
+extern int ath5k_hw_set_ack_timeout(struct ath5k_hw *ah, unsigned int timeout);
+extern unsigned int ath5k_hw_get_ack_timeout(struct ath5k_hw *ah);
+extern int ath5k_hw_set_cts_timeout(struct ath5k_hw *ah, unsigned int timeout);
+extern unsigned int ath5k_hw_get_cts_timeout(struct ath5k_hw *ah);
/* Key table (WEP) functions */
-extern int ath5k_hw_reset_key(struct ath_hw *hal, u16 entry);
-extern int ath5k_hw_is_key_valid(struct ath_hw *hal, u16 entry);
-extern int ath5k_hw_set_key(struct ath_hw *hal, u16 entry, const struct
ieee80211_key_conf *key, const u8 *mac);
-extern int ath5k_hw_set_key_lladdr(struct ath_hw *hal, u16 entry, const u8
*mac);
+extern int ath5k_hw_reset_key(struct ath5k_hw *ah, u16 entry);
+extern int ath5k_hw_is_key_valid(struct ath5k_hw *ah, u16 entry);
+extern int ath5k_hw_set_key(struct ath5k_hw *ah, u16 entry, const struct
ieee80211_key_conf *key, const u8 *mac);
+extern int ath5k_hw_set_key_lladdr(struct ath5k_hw *ah, u16 entry, const u8
*mac);
/* Queue Control Unit, DFS Control Unit Functions */
-extern int ath5k_hw_setup_tx_queue(struct ath_hw *hal, enum ath5k_tx_queue
queue_type, struct ath5k_txq_info *queue_info);
-extern int ath5k_hw_setup_tx_queueprops(struct ath_hw *hal, int queue, const
struct ath5k_txq_info *queue_info);
-extern int ath5k_hw_get_tx_queueprops(struct ath_hw *hal, int queue, struct
ath5k_txq_info *queue_info);
-extern void ath5k_hw_release_tx_queue(struct ath_hw *hal, unsigned int queue);
-extern int ath5k_hw_reset_tx_queue(struct ath_hw *hal, unsigned int queue);
-extern u32 ath5k_hw_num_tx_pending(struct ath_hw *hal, unsigned int queue);
-extern int ath5k_hw_set_slot_time(struct ath_hw *hal, unsigned int slot_time);
-extern unsigned int ath5k_hw_get_slot_time(struct ath_hw *hal);
+extern int ath5k_hw_setup_tx_queue(struct ath5k_hw *ah, enum ath5k_tx_queue
queue_type, struct ath5k_txq_info *queue_info);
+extern int ath5k_hw_setup_tx_queueprops(struct ath5k_hw *ah, int queue, const
struct ath5k_txq_info *queue_info);
+extern int ath5k_hw_get_tx_queueprops(struct ath5k_hw *ah, int queue, struct
ath5k_txq_info *queue_info);
+extern void ath5k_hw_release_tx_queue(struct ath5k_hw *ah, unsigned int queue);
+extern int ath5k_hw_reset_tx_queue(struct ath5k_hw *ah, unsigned int queue);
+extern u32 ath5k_hw_num_tx_pending(struct ath5k_hw *ah, unsigned int queue);
+extern int ath5k_hw_set_slot_time(struct ath5k_hw *ah, unsigned int slot_time);
+extern unsigned int ath5k_hw_get_slot_time(struct ath5k_hw *ah);
/* Hardware Descriptor Functions */
-extern int ath5k_hw_setup_rx_desc(struct ath_hw *hal, struct ath_desc *desc,
u32 size, unsigned int flags);
+extern int ath5k_hw_setup_rx_desc(struct ath5k_hw *ah, struct ath5k_desc
*desc, u32 size, unsigned int flags);
/* GPIO Functions */
-extern void ath5k_hw_set_ledstate(struct ath_hw *hal, unsigned int state);
-extern int ath5k_hw_set_gpio_output(struct ath_hw *hal, u32 gpio);
-extern int ath5k_hw_set_gpio_input(struct ath_hw *hal, u32 gpio);
-extern u32 ath5k_hw_get_gpio(struct ath_hw *hal, u32 gpio);
-extern int ath5k_hw_set_gpio(struct ath_hw *hal, u32 gpio, u32 val);
-extern void ath5k_hw_set_gpio_intr(struct ath_hw *hal, unsigned int gpio, u32
interrupt_level);
+extern void ath5k_hw_set_ledstate(struct ath5k_hw *ah, unsigned int state);
+extern int ath5k_hw_set_gpio_output(struct ath5k_hw *ah, u32 gpio);
+extern int ath5k_hw_set_gpio_input(struct ath5k_hw *ah, u32 gpio);
+extern u32 ath5k_hw_get_gpio(struct ath5k_hw *ah, u32 gpio);
+extern int ath5k_hw_set_gpio(struct ath5k_hw *ah, u32 gpio, u32 val);
+extern void ath5k_hw_set_gpio_intr(struct ath5k_hw *ah, unsigned int gpio, u32
interrupt_level);
/* Regulatory Domain/Channels Setup */
-extern u16 ath5k_get_regdomain(struct ath_hw *hal);
+extern u16 ath5k_get_regdomain(struct ath5k_hw *ah);
/* Misc functions */
-extern void ath5k_hw_dump_state(struct ath_hw *hal);
-extern int ath5k_hw_get_capability(struct ath_hw *hal, enum
ath5k_capability_type cap_type, u32 capability, u32 *result);
+extern void ath5k_hw_dump_state(struct ath5k_hw *ah);
+extern int ath5k_hw_get_capability(struct ath5k_hw *ah, enum
ath5k_capability_type cap_type, u32 capability, u32 *result);
/* Initial register settings functions */
-extern int ath5k_hw_write_initvals(struct ath_hw *hal, u8 mode, bool
change_channel);
+extern int ath5k_hw_write_initvals(struct ath5k_hw *ah, u8 mode, bool
change_channel);
/* Initialize RF */
-extern int ath5k_hw_rfregs(struct ath_hw *hal, struct ieee80211_channel
*channel, unsigned int mode);
-extern int ath5k_hw_rfgain(struct ath_hw *hal, unsigned int freq);
-extern enum ath5k_rfgain ath5k_hw_get_rf_gain(struct ath_hw *hal);
-extern int ath5k_hw_set_rfgain_opt(struct ath_hw *hal);
+extern int ath5k_hw_rfregs(struct ath5k_hw *ah, struct ieee80211_channel
*channel, unsigned int mode);
+extern int ath5k_hw_rfgain(struct ath5k_hw *ah, unsigned int freq);
+extern enum ath5k_rfgain ath5k_hw_get_rf_gain(struct ath5k_hw *ah);
+extern int ath5k_hw_set_rfgain_opt(struct ath5k_hw *ah);
/* PHY/RF channel functions */
-extern bool ath5k_channel_ok(struct ath_hw *hal, u16 freq, unsigned int flags);
-extern int ath5k_hw_channel(struct ath_hw *hal, struct ieee80211_channel
*channel);
+extern bool ath5k_channel_ok(struct ath5k_hw *ah, u16 freq, unsigned int
flags);
+extern int ath5k_hw_channel(struct ath5k_hw *ah, struct ieee80211_channel
*channel);
/* PHY calibration */
-extern int ath5k_hw_phy_calibrate(struct ath_hw *hal, struct ieee80211_channel
*channel);
-extern int ath5k_hw_phy_disable(struct ath_hw *hal);
+extern int ath5k_hw_phy_calibrate(struct ath5k_hw *ah, struct
ieee80211_channel *channel);
+extern int ath5k_hw_phy_disable(struct ath5k_hw *ah);
/* Misc PHY functions */
-extern u16 ath5k_hw_radio_revision(struct ath_hw *hal, unsigned int chan);
-extern void ath5k_hw_set_def_antenna(struct ath_hw *hal, unsigned int ant);
-extern unsigned int ath5k_hw_get_def_antenna(struct ath_hw *hal);
+extern u16 ath5k_hw_radio_revision(struct ath5k_hw *ah, unsigned int chan);
+extern void ath5k_hw_set_def_antenna(struct ath5k_hw *ah, unsigned int ant);
+extern unsigned int ath5k_hw_get_def_antenna(struct ath5k_hw *ah);
/* TX power setup */
-extern int ath5k_hw_txpower(struct ath_hw *hal, struct ieee80211_channel
*channel, unsigned int txpower);
-extern int ath5k_hw_set_txpower_limit(struct ath_hw *hal, unsigned int power);
+extern int ath5k_hw_txpower(struct ath5k_hw *ah, struct ieee80211_channel
*channel, unsigned int txpower);
+extern int ath5k_hw_set_txpower_limit(struct ath5k_hw *ah, unsigned int power);
-static inline u32 ath5k_hw_reg_read(struct ath_hw *hal, u16 reg)
+static inline u32 ath5k_hw_reg_read(struct ath5k_hw *ah, u16 reg)
{
- return ioread32(hal->ah_sh + reg);
+ return ioread32(ah->ah_sh + reg);
}
-static inline void ath5k_hw_reg_write(struct ath_hw *hal, u32 val, u16 reg)
+static inline void ath5k_hw_reg_write(struct ath5k_hw *ah, u32 val, u16 reg)
{
- iowrite32(val, hal->ah_sh + reg);
+ iowrite32(val, ah->ah_sh + reg);
}
#endif
Modified: ath5k/trunk/base.c
===================================================================
--- ath5k/trunk/base.c 2007-10-29 05:07:38 UTC (rev 2796)
+++ ath5k/trunk/base.c 2007-10-29 20:13:46 UTC (rev 2797)
@@ -73,7 +73,7 @@
} while (0)
#else
static inline int __attribute__ ((format (printf, 3, 4)))
-DPRINTF(struct ath_softc *sc, unsigned int m, const char *fmt, ...)
+DPRINTF(struct ath5k_softc *sc, unsigned int m, const char *fmt, ...)
{
return 0;
}
@@ -96,19 +96,17 @@
ATH_LED_RX,
};
-static int ath_calinterval = 1; /* Calibrate PHY every 1 sec (TODO: Fixme) */
+static int ath5k_calinterval = 1; /* Calibrate PHY every 1 sec (TODO: Fixme) */
#if AR_DEBUG
-static unsigned int ath_debug;
-module_param_named(debug, ath_debug, uint, 0);
+static unsigned int ath5k_debug;
+module_param_named(debug, ath5k_debug, uint, 0);
#endif
/*
- * User a static table of PCI id's for now. While this is the
- * "new way" to do things, we may want to switch back to having
- * the HAL check them by defining a probe method.
+ * Static table of PCI id's.
*/
-static struct pci_device_id ath_pci_id_table[] __devinitdata = {
+static struct pci_device_id ath5k_pci_id_table[] __devinitdata = {
{ PCI_VDEVICE(ATHEROS, 0x0207), .driver_data = AR5K_AR5210 }, /* 5210
early */
{ PCI_VDEVICE(ATHEROS, 0x0007), .driver_data = AR5K_AR5210 }, /* 5210 */
{ PCI_VDEVICE(ATHEROS, 0x0011), .driver_data = AR5K_AR5211 }, /* 5311 */
@@ -128,15 +126,15 @@
{ PCI_VDEVICE(ATHEROS, 0x001c), .driver_data = AR5K_AR5212 }, /* 5424
Condor (PCI-E)*/
{ 0 }
};
-MODULE_DEVICE_TABLE(pci, ath_pci_id_table);
+MODULE_DEVICE_TABLE(pci, ath5k_pci_id_table);
-static void ath_led_event(struct ath_softc *, int);
-static int ath_reset(struct ieee80211_hw *);
+static void ath5k_led_event(struct ath5k_softc *, int);
+static int ath5k_reset(struct ieee80211_hw *);
#if AR_DEBUG
-static void ath_printrxbuf(struct ath_buf *bf, int done)
+static void ath5k_printrxbuf(struct ath5k_buf *bf, int done)
{
- struct ath_desc *ds = bf->desc;
+ struct ath5k_desc *ds = bf->desc;
printk(KERN_DEBUG "R (%p %llx) %08x %08x %08x %08x %08x %08x %c\n",
ds, (unsigned long long)bf->daddr,
@@ -145,9 +143,9 @@
!done ? ' ' : (ds->ds_rxstat.rs_status == 0) ? '*' : '!');
}
-static void ath_printtxbuf(struct ath_buf *bf, int done)
+static void ath5k_printtxbuf(struct ath5k_buf *bf, int done)
{
- struct ath_desc *ds = bf->desc;
+ struct ath5k_desc *ds = bf->desc;
printk(KERN_DEBUG "T (%p %llx) %08x %08x %08x %08x %08x %08x %08x "
"%08x %c\n", ds, (unsigned long long)bf->daddr, ds->ds_link,
@@ -158,16 +156,16 @@
#endif
#if ATH_DUMP_SKB
-static inline void ath_dump_skb(struct sk_buff *skb, const char *prefix)
+static inline void ath5k_dump_skb(struct sk_buff *skb, const char *prefix)
{
print_hex_dump_bytes(prefix, DUMP_PREFIX_NONE, skb->data,
min(200U, skb->len));
}
#else
-static inline void ath_dump_skb(struct sk_buff *skb, const char *prefix) {}
+static inline void ath5k_dump_skb(struct sk_buff *skb, const char *prefix) {}
#endif
-static inline void ath_cleanup_txbuf(struct ath_softc *sc, struct ath_buf *bf)
+static inline void ath5k_cleanup_txbuf(struct ath5k_softc *sc, struct
ath5k_buf *bf)
{
BUG_ON(!bf);
if (!bf->skb)
@@ -178,18 +176,18 @@
bf->skb = NULL;
}
-static void ath_tasklet_reset(unsigned long data)
+static void ath5k_tasklet_reset(unsigned long data)
{
- struct ath_softc *sc = (void *)data;
+ struct ath5k_softc *sc = (void *)data;
- ath_reset(sc->hw);
+ ath5k_reset(sc->hw);
}
-static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
+static void ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq)
{
struct ieee80211_tx_status txs = {};
- struct ath_buf *bf, *bf0;
- struct ath_desc *ds;
+ struct ath5k_buf *bf, *bf0;
+ struct ath5k_desc *ds;
struct sk_buff *skb;
int ret;
@@ -244,20 +242,20 @@
ieee80211_wake_queues(sc->hw);
}
-static void ath_tasklet_tx(unsigned long data)
+static void ath5k_tasklet_tx(unsigned long data)
{
- struct ath_softc *sc = (void *)data;
+ struct ath5k_softc *sc = (void *)data;
- ath_tx_processq(sc, sc->txq);
+ ath5k_tx_processq(sc, sc->txq);
- ath_led_event(sc, ATH_LED_TX);
+ ath5k_led_event(sc, ATH_LED_TX);
}
-static int ath_rxbuf_init(struct ath_softc *sc, struct ath_buf *bf)
+static int ath5k_rxbuf_init(struct ath5k_softc *sc, struct ath5k_buf *bf)
{
- struct ath_hw *ah = sc->ah;
+ struct ath5k_hw *ah = sc->ah;
struct sk_buff *skb = bf->skb;
- struct ath_desc *ds;
+ struct ath5k_desc *ds;
if (likely(skb == NULL)) {
unsigned int off;
@@ -320,8 +318,8 @@
return 0;
}
-static unsigned int ath_rx_decrypted(struct ath_softc *sc,
- struct ath_desc *ds, struct sk_buff *skb)
+static unsigned int ath5k_rx_decrypted(struct ath5k_softc *sc,
+ struct ath5k_desc *ds, struct sk_buff *skb)
{
struct ieee80211_hdr *hdr = (void *)skb->data;
unsigned int keyix, hlen = ieee80211_get_hdrlen_from_skb(skb);
@@ -331,7 +329,7 @@
return RX_FLAG_DECRYPTED;
/* Apparently when a default key is used to decrypt the packet
- the hal does not set the index used to decrypt. In such cases
+ the hw does not set the index used to decrypt. In such cases
get the index from the packet. */
if ((le16_to_cpu(hdr->frame_control) & IEEE80211_FCTL_PROTECTED) &&
!(ds->ds_rxstat.rs_status & AR5K_RXERR_DECRYPT) &&
@@ -345,7 +343,7 @@
return 0;
}
-static inline u64 ath_extend_tsf(struct ath_hw *ah, u32 rstamp)
+static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp)
{
u64 tsf = ath5k_hw_get_tsf64(ah);
@@ -355,13 +353,13 @@
return (tsf & ~0x7fff) | rstamp;
}
-static void ath_tasklet_rx(unsigned long data)
+static void ath5k_tasklet_rx(unsigned long data)
{
struct ieee80211_rx_status rxs = {};
struct sk_buff *skb;
- struct ath_softc *sc = (void *)data;
- struct ath_buf *bf;
- struct ath_desc *ds;
+ struct ath5k_softc *sc = (void *)data;
+ struct ath5k_buf *bf;
+ struct ath5k_desc *ds;
u16 len;
u8 stat;
int ret;
@@ -375,7 +373,7 @@
printk(KERN_WARNING "ath: empty rx buf pool\n");
break;
}
- bf = list_first_entry(&sc->rxbuf, struct ath_buf, list);
+ bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
BUG_ON(bf->skb == NULL);
skb = bf->skb;
ds = bf->desc;
@@ -456,7 +454,7 @@
}
if (sc->opmode == IEEE80211_IF_TYPE_MNTR)
- rxs.mactime = ath_extend_tsf(sc->ah,
+ rxs.mactime = ath5k_extend_tsf(sc->ah,
ds->ds_rxstat.rs_tstamp);
else
rxs.mactime = ds->ds_rxstat.rs_tstamp;
@@ -466,28 +464,28 @@
rxs.ssi = ds->ds_rxstat.rs_rssi;
rxs.antenna = ds->ds_rxstat.rs_antenna;
rxs.rate = ds->ds_rxstat.rs_rate;
- rxs.flag |= ath_rx_decrypted(sc, ds, skb);
+ rxs.flag |= ath5k_rx_decrypted(sc, ds, skb);
- ath_dump_skb(skb, "RX ");
+ ath5k_dump_skb(skb, "RX ");
__ieee80211_rx(sc->hw, skb, &rxs);
sc->led_rxrate = ds->ds_rxstat.rs_rate;
- ath_led_event(sc, ATH_LED_RX);
+ ath5k_led_event(sc, ATH_LED_RX);
next:
list_move_tail(&bf->list, &sc->rxbuf);
- } while (ath_rxbuf_init(sc, bf) == 0);
+ } while (ath5k_rxbuf_init(sc, bf) == 0);
spin_unlock(&sc->rxbuflock);
}
/*
* Setup the beacon frame for transmit.
*/
-static int ath_beacon_setup(struct ath_softc *sc, struct ath_buf *bf,
+static int ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf,
struct ieee80211_tx_control *ctl)
{
struct sk_buff *skb = bf->skb;
- struct ath_hw *ah = sc->ah;
- struct ath_desc *ds;
+ struct ath5k_hw *ah = sc->ah;
+ struct ath5k_desc *ds;
int ret, antenna = 0;
u32 flags;
@@ -543,14 +541,14 @@
* frame contents are done as needed and the slot time is
* also adjusted based on current state.
*
- * this is usually called from interrupt context (ath_intr())
- * but also from ath_beacon_config() in IBSS mode which in turn
+ * this is usually called from interrupt context (ath5k_intr())
+ * but also from ath5k_beacon_config() in IBSS mode which in turn
* can be called from a tasklet and user context
*/
-static void ath_beacon_send(struct ath_softc *sc)
+static void ath5k_beacon_send(struct ath5k_softc *sc)
{
- struct ath_buf *bf = sc->bbuf;
- struct ath_hw *ah = sc->ah;
+ struct ath5k_buf *bf = sc->bbuf;
+ struct ath5k_hw *ah = sc->ah;
DPRINTF(sc, ATH_DEBUG_BEACON_PROC, "%s\n", __func__);
@@ -595,7 +593,7 @@
if (unlikely(ath5k_hw_stop_tx_dma(ah, sc->bhalq))) {
printk(KERN_WARNING "ath: beacon queue %u didn't stop?\n",
sc->bhalq);
- /* NB: the HAL still stops DMA, so proceed */
+ /* NB: hw still stops DMA, so proceed */
}
pci_dma_sync_single_for_cpu(sc->pdev, bf->skbaddr, bf->skb->len,
PCI_DMA_TODEVICE);
@@ -608,9 +606,9 @@
sc->bsent++;
}
-static int ath_beaconq_config(struct ath_softc *sc)
+static int ath5k_beaconq_config(struct ath5k_softc *sc)
{
- struct ath_hw *ah = sc->ah;
+ struct ath5k_hw *ah = sc->ah;
struct ath5k_txq_info qi;
int ret;
@@ -653,10 +651,10 @@
* interrupt when we stop seeing beacons from the AP
* we've associated with.
*/
-static void ath_beacon_config(struct ath_softc *sc)
+static void ath5k_beacon_config(struct ath5k_softc *sc)
{
#define TSF_TO_TU(_h, _l) (((_h) << 22) | ((_l) >> 10))
- struct ath_hw *ah = sc->ah;
+ struct ath5k_hw *ah = sc->ah;
u32 uninitialized_var(nexttbtt), intval, tsftu;
u64 tsf;
@@ -704,7 +702,7 @@
intval |= AR5K_BEACON_ENA;
- ath_beaconq_config(sc);
+ ath5k_beaconq_config(sc);
ath5k_hw_init_beacon(ah, nexttbtt, intval);
sc->bmisscount = 0;
@@ -715,14 +713,14 @@
*/
if (sc->opmode == IEEE80211_IF_TYPE_IBSS &&
ath5k_hw_hasveol(ah))
- ath_beacon_send(sc);
+ ath5k_beacon_send(sc);
}
#undef TSF_TO_TU
}
-static void ath_mode_init(struct ath_softc *sc)
+static void ath5k_mode_init(struct ath5k_softc *sc)
{
- struct ath_hw *ah = sc->ah;
+ struct ath5k_hw *ah = sc->ah;
u32 rfilt;
/* configure rx filter */
@@ -742,10 +740,10 @@
/*
* Enable the receive h/w following a reset.
*/
-static int ath_startrecv(struct ath_softc *sc)
+static int ath5k_startrecv(struct ath5k_softc *sc)
{
- struct ath_hw *ah = sc->ah;
- struct ath_buf *bf;
+ struct ath5k_hw *ah = sc->ah;
+ struct ath5k_buf *bf;
int ret;
sc->rxbufsize = roundup(IEEE80211_MAX_LEN, sc->cachelsz);
@@ -757,18 +755,18 @@
spin_lock_bh(&sc->rxbuflock);
list_for_each_entry(bf, &sc->rxbuf, list) {
- ret = ath_rxbuf_init(sc, bf);
+ ret = ath5k_rxbuf_init(sc, bf);
if (ret != 0) {
spin_unlock_bh(&sc->rxbuflock);
goto err;
}
}
- bf = list_first_entry(&sc->rxbuf, struct ath_buf, list);
+ bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
spin_unlock_bh(&sc->rxbuflock);
ath5k_hw_put_rx_buf(ah, bf->daddr);
ath5k_hw_start_rx(ah); /* enable recv descriptors */
- ath_mode_init(sc); /* set filters, etc. */
+ ath5k_mode_init(sc); /* set filters, etc. */
ath5k_hw_start_rx_pcu(ah); /* re-enable PCU/DMA engine */
return 0;
@@ -776,14 +774,14 @@
return ret;
}
-static inline void ath_update_txpow(struct ath_softc *sc)
+static inline void ath5k_update_txpow(struct ath5k_softc *sc)
{
ath5k_hw_set_txpower_limit(sc->ah, 0);
}
-static int ath_stop_locked(struct ath_softc *);
+static int ath5k_stop_locked(struct ath5k_softc *);
-static int ath_init(struct ath_softc *sc)
+static int ath5k_init(struct ath5k_softc *sc)
{
int ret;
@@ -795,7 +793,7 @@
* Stop anything previously setup. This is safe
* no matter this is the first time through or not.
*/
- ath_stop_locked(sc);
+ ath5k_stop_locked(sc);
/*
* The basic interface to setting the hardware in a good
@@ -814,7 +812,7 @@
* This is needed only to setup initial state
* but it's best done after a reset.
*/
- ath_update_txpow(sc);
+ ath5k_update_txpow(sc);
/*
* Setup the hardware after reset: the key cache
@@ -823,7 +821,7 @@
* in the frame output path; there's nothing to do
* here except setup the interrupt mask.
*/
- ret = ath_startrecv(sc);
+ ret = ath5k_startrecv(sc);
if (ret)
goto done;
@@ -836,7 +834,7 @@
ath5k_hw_set_intr(sc->ah, sc->imask);
mod_timer(&sc->calib_tim, round_jiffies(jiffies +
- msecs_to_jiffies(ath_calinterval * 1000)));
+ msecs_to_jiffies(ath5k_calinterval * 1000)));
ret = 0;
done:
@@ -847,9 +845,9 @@
/*
* Disable the receive h/w in preparation for a reset.
*/
-static void ath_stoprecv(struct ath_softc *sc)
+static void ath5k_stoprecv(struct ath5k_softc *sc)
{
- struct ath_hw *ah = sc->ah;
+ struct ath5k_hw *ah = sc->ah;
ath5k_hw_stop_pcu_recv(ah); /* disable PCU */
ath5k_hw_set_rx_filter(ah, 0); /* clear recv filter */
@@ -857,8 +855,8 @@
mdelay(3); /* 3ms is long enough for 1 frame */
#if AR_DEBUG
if (unlikely(sc->debug & (ATH_DEBUG_RESET | ATH_DEBUG_FATAL))) {
- struct ath_desc *ds;
- struct ath_buf *bf;
+ struct ath5k_desc *ds;
+ struct ath5k_buf *bf;
int status;
printk(KERN_DEBUG "%s: rx queue %x, link %p\n", __func__,
@@ -869,7 +867,7 @@
ds = bf->desc;
status = ah->ah_proc_rx_desc(ah, ds);
if (!status || (sc->debug & ATH_DEBUG_FATAL))
- ath_printrxbuf(bf, status == 0);
+ ath5k_printrxbuf(bf, status == 0);
}
spin_unlock_bh(&sc->rxbuflock);
}
@@ -877,22 +875,22 @@
sc->rxlink = NULL; /* just in case */
}
-static void ath_tx_draintxq(struct ath_softc *sc, struct ath_txq *txq)
+static void ath5k_tx_draintxq(struct ath5k_softc *sc, struct ath5k_txq *txq)
{
- struct ath_buf *bf, *bf0;
+ struct ath5k_buf *bf, *bf0;
/*
* NB: this assumes output has been stopped and
- * we do not need to block ath_tx_tasklet
+ * we do not need to block ath5k_tx_tasklet
*/
spin_lock_bh(&txq->lock);
list_for_each_entry_safe(bf, bf0, &txq->q, list) {
#if AR_DEBUG
if (sc->debug & ATH_DEBUG_RESET)
- ath_printtxbuf(bf, !sc->ah->ah_proc_tx_desc(sc->ah,
+ ath5k_printtxbuf(bf, !sc->ah->ah_proc_tx_desc(sc->ah,
bf->desc));
#endif
- ath_cleanup_txbuf(sc, bf);
+ ath5k_cleanup_txbuf(sc, bf);
spin_lock_bh(&sc->txbuflock);
sc->tx_stats.data[txq->qnum].len--;
@@ -907,10 +905,10 @@
/*
* Drain the transmit queues and reclaim resources.
*/
-static void ath_draintxq(struct ath_softc *sc)
+static void ath5k_draintxq(struct ath5k_softc *sc)
{
- struct ath_hw *ah = sc->ah;
- int i;
+ struct ath5k_hw *ah = sc->ah;
+ unsigned int i;
/* XXX return value */
if (likely(!test_bit(ATH_STAT_INVALID, sc->status))) {
@@ -933,12 +931,12 @@
for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
if (sc->txqs[i].setup)
- ath_tx_draintxq(sc, &sc->txqs[i]);
+ ath5k_tx_draintxq(sc, &sc->txqs[i]);
}
-static int ath_stop_locked(struct ath_softc *sc)
+static int ath5k_stop_locked(struct ath5k_softc *sc)
{
- struct ath_hw *ah = sc->ah;
+ struct ath5k_hw *ah = sc->ah;
DPRINTF(sc, ATH_DEBUG_RESET, "%s: invalid %u\n", __func__,
test_bit(ATH_STAT_INVALID, sc->status));
@@ -968,9 +966,9 @@
}
ath5k_hw_set_intr(ah, 0);
}
- ath_draintxq(sc);
+ ath5k_draintxq(sc);
if (!test_bit(ATH_STAT_INVALID, sc->status)) {
- ath_stoprecv(sc);
+ ath5k_stoprecv(sc);
ath5k_hw_phy_disable(ah);
} else
sc->rxlink = NULL;
@@ -980,16 +978,16 @@
/*
* Stop the device, grabbing the top-level lock to protect
- * against concurrent entry through ath_init (which can happen
+ * against concurrent entry through ath5k_init (which can happen
* if another thread does a system call and the thread doing the
* stop is preempted).
*/
-static int ath_stop_hw(struct ath_softc *sc)
+static int ath5k_stop_hw(struct ath5k_softc *sc)
{
int ret;
mutex_lock(&sc->lock);
- ret = ath_stop_locked(sc);
+ ret = ath5k_stop_locked(sc);
if (ret == 0 && !test_bit(ATH_STAT_INVALID, sc->status)) {
/*
* Set the chip in full sleep mode. Note that we are
@@ -1000,8 +998,7 @@
* (and system). This varies by chip and is mostly an
* issue with newer parts that go to sleep more quickly.
*/
- if (sc->ah->ah_mac_version >= 7 &&
- sc->ah->ah_mac_revision >= 8) {
+ if (sc->ah->ah_mac_srev >= 0x78) {
/*
* XXX
* don't put newer MAC revisions > 7.8 to sleep because
@@ -1015,7 +1012,7 @@
ath5k_hw_set_power(sc->ah, AR5K_PM_FULL_SLEEP, true, 0);
}
}
- ath_cleanup_txbuf(sc, sc->bbuf);
+ ath5k_cleanup_txbuf(sc, sc->bbuf);
mutex_unlock(&sc->lock);
del_timer_sync(&sc->calib_tim);
@@ -1023,7 +1020,7 @@
return ret;
}
-static void ath_setcurmode(struct ath_softc *sc, unsigned int mode)
+static void ath5k_setcurmode(struct ath5k_softc *sc, unsigned int mode)
{
if (unlikely(test_bit(ATH_STAT_LEDSOFT, sc->status))) {
/* from Atheros NDIS driver, w/ permission */
@@ -1089,11 +1086,11 @@
* Set/change channels. If the channel is really being changed,
* it's done by reseting the chip. To accomplish this we must
* first cleanup any pending DMA, then restart stuff after a la
- * ath_init.
+ * ath5k_init.
*/
-static int ath_chan_set(struct ath_softc *sc, struct ieee80211_channel *chan)
+static int ath5k_chan_set(struct ath5k_softc *sc, struct ieee80211_channel
*chan)
{
- struct ath_hw *ah = sc->ah;
+ struct ath5k_hw *ah = sc->ah;
int ret;
DPRINTF(sc, ATH_DEBUG_RESET, "%s: %u (%u MHz) -> %u (%u MHz)\n",
@@ -1108,8 +1105,8 @@
* the relevant bits of the h/w.
*/
ath5k_hw_set_intr(ah, 0); /* disable interrupts */
- ath_draintxq(sc); /* clear pending tx frames */
- ath_stoprecv(sc); /* turn off frame recv */
+ ath5k_draintxq(sc); /* clear pending tx frames */
+ ath5k_stoprecv(sc); /* turn off frame recv */
ret = ath5k_hw_reset(ah, sc->opmode, chan, true);
if (ret) {
printk(KERN_ERR "%s: unable to reset channel %u "
@@ -1117,12 +1114,12 @@
return ret;
}
sc->curchan = chan;
- ath_update_txpow(sc);
+ ath5k_update_txpow(sc);
/*
* Re-enable rx framework.
*/
- ret = ath_startrecv(sc);
+ ret = ath5k_startrecv(sc);
if (ret) {
printk(KERN_ERR "%s: unable to restart recv logic\n",
__func__);
@@ -1135,7 +1132,7 @@
*
* XXX needed?
*/
-/* ath_chan_change(sc, chan); */
+/* ath5k_chan_change(sc, chan); */
/*
* Re-enable interrupts.
@@ -1146,12 +1143,12 @@
return 0;
}
-static int ath_tx_bf(struct ath_softc *sc, struct ath_buf *bf,
+static int ath5k_tx_bf(struct ath5k_softc *sc, struct ath5k_buf *bf,
struct ieee80211_tx_control *ctl)
{
- struct ath_hw *ah = sc->ah;
- struct ath_txq *txq = sc->txq;
- struct ath_desc *ds = bf->desc;
+ struct ath5k_hw *ah = sc->ah;
+ struct ath5k_txq *txq = sc->txq;
+ struct ath5k_desc *ds = bf->desc;
struct sk_buff *skb = bf->skb;
unsigned int pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID;
int ret;
@@ -1203,16 +1200,16 @@
return ret;
}
-static int ath_tx(struct ieee80211_hw *hw, struct sk_buff *skb,
+static int ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb,
struct ieee80211_tx_control *ctl)
{
- struct ath_softc *sc = hw->priv;
- struct ath_buf *bf;
+ struct ath5k_softc *sc = hw->priv;
+ struct ath5k_buf *bf;
unsigned long flags;
int hdrlen;
int pad;
- ath_dump_skb(skb, "TX ");
+ ath5k_dump_skb(skb, "TX ");
if (sc->opmode == IEEE80211_IF_TYPE_MNTR)
DPRINTF(sc, ATH_DEBUG_XMIT, "tx in monitor (scan?)\n");
@@ -1246,7 +1243,7 @@
ieee80211_stop_queue(hw, ctl->queue);
return -1;
}
- bf = list_first_entry(&sc->txbuf, struct ath_buf, list);
+ bf = list_first_entry(&sc->txbuf, struct ath5k_buf, list);
list_del(&bf->list);
sc->txbuf_len--;
if (list_empty(&sc->txbuf))
@@ -1255,7 +1252,7 @@
bf->skb = skb;
- if (ath_tx_bf(sc, bf, ctl)) {
+ if (ath5k_tx_bf(sc, bf, ctl)) {
bf->skb = NULL;
spin_lock_irqsave(&sc->txbuflock, flags);
list_add_tail(&bf->list, &sc->txbuf);
@@ -1268,31 +1265,31 @@
return 0;
}
-static int ath_reset(struct ieee80211_hw *hw)
+static int ath5k_reset(struct ieee80211_hw *hw)
{
- struct ath_softc *sc = hw->priv;
- struct ath_hw *ah = sc->ah;
+ struct ath5k_softc *sc = hw->priv;
+ struct ath5k_hw *ah = sc->ah;
int ret;
DPRINTF(sc, ATH_DEBUG_RESET, "resetting\n");
/*
- * Convert to a HAL channel description with the flags
+ * Convert to a hw channel description with the flags
* constrained to reflect the current operating mode.
*/
sc->curchan = hw->conf.chan;
ath5k_hw_set_intr(ah, 0);
- ath_draintxq(sc);
- ath_stoprecv(sc);
+ ath5k_draintxq(sc);
+ ath5k_stoprecv(sc);
ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, true);
if (unlikely(ret)) {
printk(KERN_ERR "ath: can't reset hardware (%d)\n", ret);
goto err;
}
- ath_update_txpow(sc);
+ ath5k_update_txpow(sc);
- ret = ath_startrecv(sc);
+ ret = ath5k_startrecv(sc);
if (unlikely(ret)) {
printk(KERN_ERR "ath: can't start recv logic\n");
goto err;
@@ -1304,9 +1301,9 @@
*
* XXX needed?
*/
-/* ath_chan_change(sc, c); */
- ath_beacon_config(sc);
- /* intrs are started by ath_beacon_config */
+/* ath5k_chan_change(sc, c); */
+ ath5k_beacon_config(sc);
+ /* intrs are started by ath5k_beacon_config */
ieee80211_wake_queues(hw);
@@ -1315,20 +1312,20 @@
return ret;
}
-static int ath_start(struct ieee80211_hw *hw)
+static int ath5k_start(struct ieee80211_hw *hw)
{
- return ath_init(hw->priv);
+ return ath5k_init(hw->priv);
}
-void ath_stop(struct ieee80211_hw *hw)
+static void ath5k_stop(struct ieee80211_hw *hw)
{
- ath_stop_hw(hw->priv);
+ ath5k_stop_hw(hw->priv);
}
-static int ath_add_interface(struct ieee80211_hw *hw,
+static int ath5k_add_interface(struct ieee80211_hw *hw,
struct ieee80211_if_init_conf *conf)
{
- struct ath_softc *sc = hw->priv;
+ struct ath5k_softc *sc = hw->priv;
int ret;
mutex_lock(&sc->lock);
@@ -1355,10 +1352,10 @@
return ret;
}
-static void ath_remove_interface(struct ieee80211_hw *hw,
+static void ath5k_remove_interface(struct ieee80211_hw *hw,
struct ieee80211_if_init_conf *conf)
{
- struct ath_softc *sc = hw->priv;
+ struct ath5k_softc *sc = hw->priv;
mutex_lock(&sc->lock);
if (sc->iface_id != conf->if_id)
@@ -1369,25 +1366,25 @@
mutex_unlock(&sc->lock);
}
-static int ath_config(struct ieee80211_hw *hw, struct ieee80211_conf *conf)
+static int ath5k_config(struct ieee80211_hw *hw, struct ieee80211_conf *conf)
{
- struct ath_softc *sc = hw->priv;
+ struct ath5k_softc *sc = hw->priv;
sc->bintval = conf->beacon_int * 1000 / 1024;
- ath_setcurmode(sc, conf->phymode);
+ ath5k_setcurmode(sc, conf->phymode);
- return ath_chan_set(sc, conf->chan);
+ return ath5k_chan_set(sc, conf->chan);
}
-static int ath_config_interface(struct ieee80211_hw *hw, int if_id,
+static int ath5k_config_interface(struct ieee80211_hw *hw, int if_id,
struct ieee80211_if_conf *conf)
{
- struct ath_softc *sc = hw->priv;
- struct ath_hw *ah = sc->ah;
+ struct ath5k_softc *sc = hw->priv;
+ struct ath5k_hw *ah = sc->ah;
int ret;
/* Set to a reasonable value. Note that this will
- * be set to mac80211's value at ath_config(). */
+ * be set to mac80211's value at ath5k_config(). */
sc->bintval = 1000 * 1000 / 1024;
mutex_lock(&sc->lock);
if (sc->iface_id != if_id) {
@@ -1403,7 +1400,7 @@
}
mutex_unlock(&sc->lock);
- return ath_reset(hw);
+ return ath5k_reset(hw);
unlock:
mutex_unlock(&sc->lock);
return ret;
@@ -1431,13 +1428,12 @@
* the station is otherwise quiet, or
* - when scanning
*/
-static void ath_configure_filter(struct ieee80211_hw *hw,
- unsigned int changed_flags,
- unsigned int *new_flags,
- int mc_count, struct dev_mc_list *mclist)
+static void ath5k_configure_filter(struct ieee80211_hw *hw,
+ unsigned int changed_flags, unsigned int *new_flags,
+ int mc_count, struct dev_mc_list *mclist)
{
- struct ath_softc *sc = hw->priv;
- struct ath_hw *ah = sc->ah;
+ struct ath5k_softc *sc = hw->priv;
+ struct ath5k_hw *ah = sc->ah;
u32 mfilt[2], val, rfilt;
u8 pos;
int i;
@@ -1530,11 +1526,11 @@
sc->filter_flags = rfilt;
}
-static int ath_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
+static int ath5k_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
const u8 *local_addr, const u8 *addr,
struct ieee80211_key_conf *key)
{
- struct ath_softc *sc = hw->priv;
+ struct ath5k_softc *sc = hw->priv;
int ret = 0;
switch(key->alg) {
@@ -1574,47 +1570,47 @@
return ret;
}
-static int ath_get_stats(struct ieee80211_hw *hw,
+static int ath5k_get_stats(struct ieee80211_hw *hw,
struct ieee80211_low_level_stats *stats)
{
- struct ath_softc *sc = hw->priv;
+ struct ath5k_softc *sc = hw->priv;
memcpy(stats, &sc->ll_stats, sizeof(sc->ll_stats));
return 0;
}
-static int ath_get_tx_stats(struct ieee80211_hw *hw,
+static int ath5k_get_tx_stats(struct ieee80211_hw *hw,
struct ieee80211_tx_queue_stats *stats)
{
- struct ath_softc *sc = hw->priv;
+ struct ath5k_softc *sc = hw->priv;
memcpy(stats, &sc->tx_stats, sizeof(sc->tx_stats));
return 0;
}
-static u64 ath_get_tsf(struct ieee80211_hw *hw)
+static u64 ath5k_get_tsf(struct ieee80211_hw *hw)
{
- struct ath_softc *sc = hw->priv;
+ struct ath5k_softc *sc = hw->priv;
return ath5k_hw_get_tsf64(sc->ah);
}
-static void ath_reset_tsf(struct ieee80211_hw *hw)
+static void ath5k_reset_tsf(struct ieee80211_hw *hw)
{
- struct ath_softc *sc = hw->priv;
+ struct ath5k_softc *sc = hw->priv;
ath5k_hw_reset_tsf(sc->ah);
}
-static int ath_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb,
+static int ath5k_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb,
struct ieee80211_tx_control *ctl)
{
- struct ath_softc *sc = hw->priv;
+ struct ath5k_softc *sc = hw->priv;
int ret;
- ath_dump_skb(skb, "BC ");
+ ath5k_dump_skb(skb, "BC ");
mutex_lock(&sc->lock);
@@ -1623,9 +1619,9 @@
goto end;
}
- ath_cleanup_txbuf(sc, sc->bbuf);
+ ath5k_cleanup_txbuf(sc, sc->bbuf);
sc->bbuf->skb = skb;
- ret = ath_beacon_setup(sc, sc->bbuf, ctl);
+ ret = ath5k_beacon_setup(sc, sc->bbuf, ctl);
if (ret)
sc->bbuf->skb = NULL;
@@ -1634,32 +1630,32 @@
return ret;
}
-static struct ieee80211_ops ath_hw_ops = {
- .tx = ath_tx,
- .start = ath_start,
- .stop = ath_stop,
- .add_interface = ath_add_interface,
- .remove_interface = ath_remove_interface,
- .config = ath_config,
- .config_interface = ath_config_interface,
- .configure_filter = ath_configure_filter,
- .set_key = ath_set_key,
- .get_stats = ath_get_stats,
+static struct ieee80211_ops ath5k_hw_ops = {
+ .tx = ath5k_tx,
+ .start = ath5k_start,
+ .stop = ath5k_stop,
+ .add_interface = ath5k_add_interface,
+ .remove_interface = ath5k_remove_interface,
+ .config = ath5k_config,
+ .config_interface = ath5k_config_interface,
+ .configure_filter = ath5k_configure_filter,
+ .set_key = ath5k_set_key,
+ .get_stats = ath5k_get_stats,
.conf_tx = NULL,
- .get_tx_stats = ath_get_tx_stats,
- .get_tsf = ath_get_tsf,
- .reset_tsf = ath_reset_tsf,
- .beacon_update = ath_beacon_update,
+ .get_tx_stats = ath5k_get_tx_stats,
+ .get_tsf = ath5k_get_tsf,
+ .reset_tsf = ath5k_reset_tsf,
+ .beacon_update = ath5k_beacon_update,
};
/*
* Periodically recalibrate the PHY to account
* for temperature/environment changes.
*/
-static void ath_calibrate(unsigned long data)
+static void ath5k_calibrate(unsigned long data)
{
- struct ath_softc *sc = (void *)data;
- struct ath_hw *ah = sc->ah;
+ struct ath5k_softc *sc = (void *)data;
+ struct ath5k_hw *ah = sc->ah;
DPRINTF(sc, ATH_DEBUG_CALIBRATE, "ath: channel %u/%x\n",
sc->curchan->chan, sc->curchan->val);
@@ -1670,19 +1666,19 @@
* to load new gain values.
*/
DPRINTF(sc, ATH_DEBUG_RESET, "calibration, resetting\n");
- ath_reset(sc->hw);
+ ath5k_reset(sc->hw);
}
if (ath5k_hw_phy_calibrate(ah, sc->curchan))
printk(KERN_ERR "ath: calibration of channel %u failed\n",
sc->curchan->chan);
mod_timer(&sc->calib_tim, round_jiffies(jiffies +
- msecs_to_jiffies(ath_calinterval * 1000)));
+ msecs_to_jiffies(ath5k_calinterval * 1000)));
}
-static void ath_led_off(unsigned long data)
+static void ath5k_led_off(unsigned long data)
{
- struct ath_softc *sc = (void *)data;
+ struct ath5k_softc *sc = (void *)data;
if (test_bit(ATH_STAT_LEDENDBLINK, sc->status))
__clear_bit(ATH_STAT_LEDBLINKING, sc->status);
@@ -1696,7 +1692,7 @@
/*
* Blink the LED according to the specified on/off times.
*/
-static void ath_led_blink(struct ath_softc *sc, unsigned int on,
+static void ath5k_led_blink(struct ath5k_softc *sc, unsigned int on,
unsigned int off)
{
DPRINTF(sc, ATH_DEBUG_LED, "%s: on %u off %u\n", __func__, on, off);
@@ -1707,7 +1703,7 @@
mod_timer(&sc->led_tim, jiffies + on);
}
-static void ath_led_event(struct ath_softc *sc, int event)
+static void ath5k_led_event(struct ath5k_softc *sc, int event)
{
if (likely(!test_bit(ATH_STAT_LEDSOFT, sc->status)))
return;
@@ -1715,20 +1711,20 @@
return; /* don't interrupt active blink */
switch (event) {
case ATH_LED_TX:
- ath_led_blink(sc, sc->hwmap[sc->led_txrate].ledon,
+ ath5k_led_blink(sc, sc->hwmap[sc->led_txrate].ledon,
sc->hwmap[sc->led_txrate].ledoff);
break;
case ATH_LED_RX:
- ath_led_blink(sc, sc->hwmap[sc->led_rxrate].ledon,
+ ath5k_led_blink(sc, sc->hwmap[sc->led_rxrate].ledon,
sc->hwmap[sc->led_rxrate].ledoff);
break;
}
}
-static irqreturn_t ath_intr(int irq, void *dev_id)
+static irqreturn_t ath5k_intr(int irq, void *dev_id)
{
- struct ath_softc *sc = dev_id;
- struct ath_hw *ah = sc->ah;
+ struct ath5k_softc *sc = dev_id;
+ struct ath5k_hw *ah = sc->ah;
enum ath5k_int status;
unsigned int counter = 1000;
@@ -1738,22 +1734,20 @@
do {
/*
- * Figure out the reason(s) for the interrupt. Note
- * that the hal returns a pseudo-ISR that may include
- * bits we haven't explicitly enabled so we mask the
- * value to insure we only process bits we requested.
- */
+ * Figure out the reason(s) for the interrupt. Note
+ * that get_isr returns a pseudo-ISR that may include
+ * bits we haven't explicitly enabled so we mask the
+ * value to insure we only process bits we requested.
+ */
ath5k_hw_get_isr(ah, &status); /* NB: clears IRQ too */
DPRINTF(sc, ATH_DEBUG_INTR, "%s: status 0x%x/0x%x\n", __func__,
status, sc->imask);
status &= sc->imask; /* discard unasked for bits */
if (unlikely(status & AR5K_INT_FATAL)) {
/*
- * Fatal errors are unrecoverable. Typically
- * these are caused by DMA errors. Unfortunately
- * the exact reason is not (presently) returned
- * by the hal.
- */
+ * Fatal errors are unrecoverable.
+ * Typically these are caused by DMA errors.
+ */
tasklet_schedule(&sc->restq);
} else if (unlikely(status & AR5K_INT_RXORN)) {
tasklet_schedule(&sc->restq);
@@ -1765,7 +1759,7 @@
* this is too slow to meet timing constraints
* under load.
*/
- ath_beacon_send(sc);
+ ath5k_beacon_send(sc);
}
if (status & AR5K_INT_RXEOL) {
/*
@@ -1801,7 +1795,7 @@
/*
* Convert IEEE channel number to MHz frequency.
*/
-static inline short ath_ieee2mhz(short chan)
+static inline short ath5k_ieee2mhz(short chan)
{
if (chan <= 14 || chan >= 27)
return ieee80211chan2mhz(chan);
@@ -1809,7 +1803,7 @@
return 2212 + chan * 20;
}
-static unsigned int ath_copy_rates(struct ieee80211_rate *rates,
+static unsigned int ath5k_copy_rates(struct ieee80211_rate *rates,
const struct ath5k_rate_table *rt, unsigned int max)
{
unsigned int i, count;
@@ -1831,7 +1825,7 @@
return count;
}
-static unsigned int ath_copy_channels(struct ath_hw *ah,
+static unsigned int ath5k_copy_channels(struct ath5k_hw *ah,
struct ieee80211_channel *channels, unsigned int mode,
unsigned int max)
{
@@ -1881,7 +1875,7 @@
for (i = 0, count = 0; i < size && max > 0; i++) {
ch = all ? i + 1 : chans[i].chan;
- f = ath_ieee2mhz(ch);
+ f = ath5k_ieee2mhz(ch);
/* Check if channel is supported by the chipset */
if (!ath5k_channel_ok(ah, f, chfreq))
continue;
@@ -1907,7 +1901,7 @@
}
#if ATH_DEBUG_MODES
-static void ath_dump_modes(struct ieee80211_hw_mode *modes)
+static void ath5k_dump_modes(struct ieee80211_hw_mode *modes)
{
unsigned int m, i;
@@ -1931,15 +1925,19 @@
}
}
#else
-static inline void ath_dump_modes(struct ieee80211_hw_mode *modes) {}
+static inline void ath5k_dump_modes(struct ieee80211_hw_mode *modes) {}
#endif
static inline int ath5k_register_mode(struct ieee80211_hw *hw, u8 m)
{
- struct ath_softc *sc = hw->priv;
+ struct ath5k_softc *sc = hw->priv;
struct ieee80211_hw_mode *modes = sc->modes;
- int i, ret;
+ unsigned int i;
+ int ret;
+ if (!test_bit(m, sc->ah->ah_capabilities.cap_mode))
+ return 0;
+
for (i = 0; i < NUM_DRIVER_MODES; i++) {
if (modes[i].mode != m || !modes[i].num_channels)
continue;
@@ -1950,22 +1948,20 @@
}
return 0;
}
- return 1;
+ BUG();
}
/* Only tries to register modes our EEPROM says it can support */
#define REGISTER_MODE(m) do { \
- if (test_bit(m, ah->ah_capabilities.cap_mode)) { \
- ret = ath5k_register_mode(hw, m); \
- if (ret) \
- return ret; \
- } \
+ ret = ath5k_register_mode(hw, m); \
+ if (ret) \
+ return ret; \
} while (0) \
-static int ath_getchannels(struct ieee80211_hw *hw)
+static int ath5k_getchannels(struct ieee80211_hw *hw)
{
- struct ath_softc *sc = hw->priv;
- struct ath_hw *ah = sc->ah;
+ struct ath5k_softc *sc = hw->priv;
+ struct ath5k_hw *ah = sc->ah;
struct ieee80211_hw_mode *modes = sc->modes;
unsigned int i, max_r, max_c;
int ret;
@@ -1996,12 +1992,9 @@
}
hw_rates = ath5k_hw_get_rate_table(ah, mode->mode);
- if (!hw_rates)
- return -EINVAL;
-
- mode->num_rates = ath_copy_rates(mode->rates, hw_rates,
+ mode->num_rates = ath5k_copy_rates(mode->rates, hw_rates,
max_r);
- mode->num_channels = ath_copy_channels(ah, mode->channels,
+ mode->num_channels = ath5k_copy_channels(ah, mode->channels,
mode->mode, max_c);
max_r -= mode->num_rates;
max_c -= mode->num_channels;
@@ -2019,21 +2012,21 @@
REGISTER_MODE(MODE_IEEE80211B);
REGISTER_MODE(MODE_IEEE80211A);
- ath_dump_modes(modes);
+ ath5k_dump_modes(modes);
return ret;
}
-static int ath_desc_alloc(struct ath_softc *sc, struct pci_dev *pdev)
+static int ath5k_desc_alloc(struct ath5k_softc *sc, struct pci_dev *pdev)
{
- struct ath_desc *ds;
- struct ath_buf *bf;
+ struct ath5k_desc *ds;
+ struct ath5k_buf *bf;
dma_addr_t da;
unsigned int i;
int ret;
/* allocate descriptors */
- sc->desc_len = sizeof(struct ath_desc) *
+ sc->desc_len = sizeof(struct ath5k_desc) *
(ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1);
sc->desc = pci_alloc_consistent(pdev, sc->desc_len, &sc->desc_daddr);
if (sc->desc == NULL) {
@@ -2047,7 +2040,7 @@
__func__, ds, sc->desc_len, (unsigned long long)sc->desc_daddr);
bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF,
- sizeof(struct ath_buf), GFP_KERNEL);
+ sizeof(struct ath5k_buf), GFP_KERNEL);
if (bf == NULL) {
dev_err(&pdev->dev, "can't allocate bufptr\n");
ret = -ENOMEM;
@@ -2084,15 +2077,15 @@
return ret;
}
-static void ath_desc_free(struct ath_softc *sc, struct pci_dev *pdev)
+static void ath5k_desc_free(struct ath5k_softc *sc, struct pci_dev *pdev)
{
- struct ath_buf *bf;
+ struct ath5k_buf *bf;
- ath_cleanup_txbuf(sc, sc->bbuf);
+ ath5k_cleanup_txbuf(sc, sc->bbuf);
list_for_each_entry(bf, &sc->txbuf, list)
- ath_cleanup_txbuf(sc, bf);
+ ath5k_cleanup_txbuf(sc, bf);
list_for_each_entry(bf, &sc->rxbuf, list)
- ath_cleanup_txbuf(sc, bf);
+ ath5k_cleanup_txbuf(sc, bf);
/* Free memory associated with all descriptors */
pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
@@ -2101,7 +2094,7 @@
sc->bufptr = NULL;
}
-static int ath_beaconq_setup(struct ath_hw *ah)
+static int ath5k_beaconq_setup(struct ath5k_hw *ah)
{
struct ath5k_txq_info qi = {
.tqi_aifs = AR5K_TXQ_USEDEFAULT,
@@ -2114,11 +2107,11 @@
return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi);
}
-static struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype,
+static struct ath5k_txq *ath5k_txq_setup(struct ath5k_softc *sc, int qtype,
int subtype)
{
- struct ath_hw *ah = sc->ah;
- struct ath_txq *txq;
+ struct ath5k_hw *ah = sc->ah;
+ struct ath5k_txq *txq;
struct ath5k_txq_info qi = {
.tqi_subtype = subtype,
.tqi_aifs = AR5K_TXQ_USEDEFAULT,
@@ -2150,7 +2143,7 @@
return ERR_PTR(qnum);
}
if (qnum >= ARRAY_SIZE(sc->txqs)) {
- printk(KERN_ERR "hal qnum %u out of range, max %tu!\n",
+ printk(KERN_ERR "hw qnum %u out of range, max %tu!\n",
qnum, ARRAY_SIZE(sc->txqs));
ath5k_hw_release_tx_queue(ah, qnum);
return ERR_PTR(-EINVAL);
@@ -2166,9 +2159,9 @@
return &sc->txqs[qnum];
}
-static void ath_tx_cleanup(struct ath_softc *sc)
+static void ath5k_tx_cleanup(struct ath5k_softc *sc)
{
- struct ath_txq *txq = sc->txqs;
+ struct ath5k_txq *txq = sc->txqs;
unsigned int i;
for (i = 0; i < ARRAY_SIZE(sc->txqs); i++, txq++)
@@ -2178,10 +2171,10 @@
}
}
-static int ath_attach(struct pci_dev *pdev, struct ieee80211_hw *hw)
+static int ath5k_attach(struct pci_dev *pdev, struct ieee80211_hw *hw)
{
- struct ath_softc *sc = hw->priv;
- struct ath_hw *ah = sc->ah;
+ struct ath5k_softc *sc = hw->priv;
+ struct ath5k_hw *ah = sc->ah;
u8 mac[ETH_ALEN];
unsigned int i;
int ret;
@@ -2211,22 +2204,22 @@
* on settings like the phy mode and regulatory
* domain restrictions.
*/
- ret = ath_getchannels(hw);
+ ret = ath5k_getchannels(hw);
if (ret) {
dev_err(&pdev->dev, "can't get channels\n");
goto err;
}
- /* NB: setup here so ath_rate_update is happy */
+ /* NB: setup here so ath5k_rate_update is happy */
if (test_bit(MODE_IEEE80211A, ah->ah_modes))
- ath_setcurmode(sc, MODE_IEEE80211A);
+ ath5k_setcurmode(sc, MODE_IEEE80211A);
else
- ath_setcurmode(sc, MODE_IEEE80211B);
+ ath5k_setcurmode(sc, MODE_IEEE80211B);
/*
* Allocate tx+rx descriptors and populate the lists.
*/
- ret = ath_desc_alloc(sc, pdev);
+ ret = ath5k_desc_alloc(sc, pdev);
if (ret) {
dev_err(&pdev->dev, "can't allocate descriptors\n");
goto err;
@@ -2235,28 +2228,28 @@
/*
* Allocate hardware transmit queues: one queue for
* beacon frames and one data queue for each QoS
- * priority. Note that the hal handles reseting
+ * priority. Note that hw functions handle reseting
* these queues at the needed time.
*/
- ret = ath_beaconq_setup(ah);
+ ret = ath5k_beaconq_setup(ah);
if (ret < 0) {
dev_err(&pdev->dev, "can't setup a beacon xmit queue\n");
goto err_desc;
}
sc->bhalq = ret;
- sc->txq = ath_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK);
+ sc->txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK);
if (IS_ERR(sc->txq)) {
dev_err(&pdev->dev, "can't setup xmit queue\n");
ret = PTR_ERR(sc->txq);
goto err_bhal;
}
- tasklet_init(&sc->rxtq, ath_tasklet_rx, (unsigned long)sc);
- tasklet_init(&sc->txtq, ath_tasklet_tx, (unsigned long)sc);
- tasklet_init(&sc->restq, ath_tasklet_reset, (unsigned long)sc);
- setup_timer(&sc->calib_tim, ath_calibrate, (unsigned long)sc);
- setup_timer(&sc->led_tim, ath_led_off, (unsigned long)sc);
+ tasklet_init(&sc->rxtq, ath5k_tasklet_rx, (unsigned long)sc);
+ tasklet_init(&sc->txtq, ath5k_tasklet_tx, (unsigned long)sc);
+ tasklet_init(&sc->restq, ath5k_tasklet_reset, (unsigned long)sc);
+ setup_timer(&sc->calib_tim, ath5k_calibrate, (unsigned long)sc);
+ setup_timer(&sc->led_tim, ath5k_led_off, (unsigned long)sc);
sc->led_on = 0; /* low true */
/*
@@ -2293,22 +2286,22 @@
return 0;
err_queues:
- ath_tx_cleanup(sc);
+ ath5k_tx_cleanup(sc);
err_bhal:
ath5k_hw_release_tx_queue(ah, sc->bhalq);
err_desc:
- ath_desc_free(sc, pdev);
+ ath5k_desc_free(sc, pdev);
err:
return ret;
}
-static void ath_detach(struct pci_dev *pdev, struct ieee80211_hw *hw)
+static void ath5k_detach(struct pci_dev *pdev, struct ieee80211_hw *hw)
{
- struct ath_softc *sc = hw->priv;
+ struct ath5k_softc *sc = hw->priv;
/*
* NB: the order of these is important:
- * o call the 802.11 layer before detaching the hal to
+ * o call the 802.11 layer before detaching ath5k_hw to
* insure callbacks into the driver to delete global
* key cache entries can be handled
* o reclaim the tx queue data structures after calling
@@ -2316,11 +2309,12 @@
* node state and potentially want to use them
* o to cleanup the tx queues the hal is called, so detach
* it last
+ * XXX: ??? detach ath5k_hw ???
* Other than that, it's straightforward...
*/
ieee80211_unregister_hw(hw);
- ath_desc_free(sc, pdev);
- ath_tx_cleanup(sc);
+ ath5k_desc_free(sc, pdev);
+ ath5k_tx_cleanup(sc);
ath5k_hw_release_tx_queue(sc->ah, sc->bhalq);
/*
@@ -2330,7 +2324,7 @@
*/
}
-static const char *ath_chip_name(u8 mac_version)
+static const char *ath5k_chip_name(u8 mac_version)
{
switch (mac_version) {
case AR5K_AR5210:
@@ -2343,11 +2337,11 @@
return "Unknown";
}
-static int __devinit ath_pci_probe(struct pci_dev *pdev,
+static int __devinit ath5k_pci_probe(struct pci_dev *pdev,
const struct pci_device_id *id)
{
void __iomem *mem;
- struct ath_softc *sc;
+ struct ath5k_softc *sc;
struct ieee80211_hw *hw;
int ret;
u8 csz;
@@ -2409,7 +2403,7 @@
goto err_reg;
}
- hw = ieee80211_alloc_hw(sizeof(*sc), &ath_hw_ops);
+ hw = ieee80211_alloc_hw(sizeof(*sc), &ath5k_hw_ops);
if (hw == NULL) {
dev_err(&pdev->dev, "cannot allocate ieee80211_hw\n");
ret = -ENOMEM;
@@ -2430,7 +2424,7 @@
* interrupts until setup is complete.
*/
#if AR_DEBUG
- sc->debug = ath_debug;
+ sc->debug = ath5k_debug;
#endif
__set_bit(ATH_STAT_INVALID, sc->status);
sc->iobase = mem;
@@ -2444,7 +2438,7 @@
pci_enable_msi(pdev);
- ret = request_irq(pdev->irq, ath_intr, IRQF_SHARED, "ath", sc);
+ ret = request_irq(pdev->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
if (ret) {
dev_err(&pdev->dev, "request_irq failed\n");
goto err_free;
@@ -2456,13 +2450,13 @@
goto err_irq;
}
- ret = ath_attach(pdev, hw);
+ ret = ath5k_attach(pdev, hw);
if (ret)
goto err_ah;
dev_info(&pdev->dev, "%s chip found: mac %d.%d phy %d.%d\n",
- ath_chip_name(id->driver_data), sc->ah->ah_mac_version,
- sc->ah->ah_mac_version, sc->ah->ah_phy_revision >> 4,
+ ath5k_chip_name(id->driver_data),
sc->ah->ah_mac_version,
+ sc->ah->ah_mac_revision, sc->ah->ah_phy_revision >> 4,
sc->ah->ah_phy_revision & 0xf);
/* ready to process interrupts */
@@ -2486,12 +2480,12 @@
return ret;
}
-static void __devexit ath_pci_remove(struct pci_dev *pdev)
+static void __devexit ath5k_pci_remove(struct pci_dev *pdev)
{
struct ieee80211_hw *hw = pci_get_drvdata(pdev);
- struct ath_softc *sc = hw->priv;
+ struct ath5k_softc *sc = hw->priv;
- ath_detach(pdev, hw);
+ ath5k_detach(pdev, hw);
ath5k_hw_detach(sc->ah);
free_irq(pdev->irq, sc);
pci_disable_msi(pdev);
@@ -2502,15 +2496,15 @@
}
#ifdef CONFIG_PM
-static int ath_pci_suspend(struct pci_dev *pdev, pm_message_t state)
+static int ath5k_pci_suspend(struct pci_dev *pdev, pm_message_t state)
{
struct ieee80211_hw *hw = pci_get_drvdata(pdev);
- struct ath_softc *sc = hw->priv;
+ struct ath5k_softc *sc = hw->priv;
if (test_bit(ATH_STAT_LEDSOFT, sc->status))
ath5k_hw_set_gpio(sc->ah, sc->led_pin, 1);
- ath_stop_hw(sc);
+ ath5k_stop_hw(sc);
pci_save_state(pdev);
pci_disable_device(pdev);
pci_set_power_state(pdev, PCI_D3hot);
@@ -2518,10 +2512,10 @@
return 0;
}
-static int ath_pci_resume(struct pci_dev *pdev)
+static int ath5k_pci_resume(struct pci_dev *pdev)
{
struct ieee80211_hw *hw = pci_get_drvdata(pdev);
- struct ath_softc *sc = hw->priv;
+ struct ath5k_softc *sc = hw->priv;
int err;
err = pci_set_power_state(pdev, PCI_D0);
@@ -2540,7 +2534,7 @@
*/
pci_write_config_byte(pdev, 0x41, 0);
- ath_init(sc);
+ ath5k_init(sc);
if (test_bit(ATH_STAT_LEDSOFT, sc->status)) {
ath5k_hw_set_gpio_output(sc->ah, sc->led_pin);
ath5k_hw_set_gpio(sc->ah, sc->led_pin, 0);
@@ -2549,84 +2543,84 @@
return 0;
}
#else
-#define ath_pci_suspend NULL
-#define ath_pci_resume NULL
+#define ath5k_pci_suspend NULL
+#define ath5k_pci_resume NULL
#endif /* CONFIG_PM */
-static struct pci_driver ath_pci_drv_id = {
- .name = "ath_pci",
- .id_table = ath_pci_id_table,
- .probe = ath_pci_probe,
- .remove = __devexit_p(ath_pci_remove),
- .suspend = ath_pci_suspend,
- .resume = ath_pci_resume,
+static struct pci_driver ath5k_pci_drv_id = {
+ .name = "ath5k_pci",
+ .id_table = ath5k_pci_id_table,
+ .probe = ath5k_pci_probe,
+ .remove = __devexit_p(ath5k_pci_remove),
+ .suspend = ath5k_pci_suspend,
+ .resume = ath5k_pci_resume,
};
static int mincalibrate = 1;
static int maxcalibrate = INT_MAX / 1000;
#define CTL_AUTO -2 /* cannot be CTL_ANY or CTL_NONE */
-static ctl_table ath_static_sysctls[] = {
+static ctl_table ath5k_static_sysctls[] = {
#if AR_DEBUG
{
.procname = "debug",
.mode = 0644,
- .data = &ath_debug,
- .maxlen = sizeof(ath_debug),
+ .data = &ath5k_debug,
+ .maxlen = sizeof(ath5k_debug),
.proc_handler = proc_dointvec
},
#endif
{
.procname = "calibrate",
.mode = 0644,
- .data = &ath_calinterval,
- .maxlen = sizeof(ath_calinterval),
+ .data = &ath5k_calinterval,
+ .maxlen = sizeof(ath5k_calinterval),
.extra1 = &mincalibrate,
.extra2 = &maxcalibrate,
.proc_handler = proc_dointvec_minmax
},
{ 0 }
};
-static ctl_table ath_ath_table[] = {
+static ctl_table ath5k_ath5k_table[] = {
{
.procname = "ath",
.mode = 0555,
- .child = ath_static_sysctls
+ .child = ath5k_static_sysctls
}, { 0 }
};
-static ctl_table ath_root_table[] = {
+static ctl_table ath5k_root_table[] = {
{
.ctl_name = CTL_DEV,
.procname = "dev",
.mode = 0555,
- .child = ath_ath_table
+ .child = ath5k_ath5k_table
}, { 0 }
};
-static struct ctl_table_header *ath_sysctl_header;
+static struct ctl_table_header *ath5k_sysctl_header;
-static int __init init_ath_pci(void)
+static int __init init_ath5k_pci(void)
{
int ret;
- ret = pci_register_driver(&ath_pci_drv_id);
+ ret = pci_register_driver(&ath5k_pci_drv_id);
if (ret) {
- printk(KERN_ERR "ath_pci: can't register pci driver\n");
+ printk(KERN_ERR "ath5k_pci: can't register pci driver\n");
return ret;
}
- ath_sysctl_header = register_sysctl_table(ath_root_table);
+ ath5k_sysctl_header = register_sysctl_table(ath5k_root_table);
return 0;
}
-static void __exit exit_ath_pci(void)
+static void __exit exit_ath5k_pci(void)
{
- if (ath_sysctl_header)
- unregister_sysctl_table(ath_sysctl_header);
- pci_unregister_driver(&ath_pci_drv_id);
+ if (ath5k_sysctl_header)
+ unregister_sysctl_table(ath5k_sysctl_header);
+ pci_unregister_driver(&ath5k_pci_drv_id);
}
-module_init(init_ath_pci);
-module_exit(exit_ath_pci);
+module_init(init_ath5k_pci);
+module_exit(exit_ath5k_pci);
MODULE_AUTHOR("Jiri Slaby");
MODULE_DESCRIPTION("Support for Atheros 802.11 wireless LAN cards.");
Modified: ath5k/trunk/base.h
===================================================================
--- ath5k/trunk/base.h 2007-10-29 05:07:38 UTC (rev 2796)
+++ ath5k/trunk/base.h 2007-10-29 20:13:46 UTC (rev 2797)
@@ -52,10 +52,10 @@
#define ATH_TXBUF 200 /* number of TX buffers */
#define ATH_BCBUF 1 /* number of beacon buffers */
-struct ath_buf {
+struct ath5k_buf {
struct list_head list;
unsigned int flags; /* tx descriptor flags */
- struct ath_desc *desc; /* virtual addr of desc */
+ struct ath5k_desc *desc; /* virtual addr of desc */
dma_addr_t daddr; /* physical addr of desc */
struct sk_buff *skb; /* skbuff for buf */
dma_addr_t skbaddr;/* physical addr of skb data */
@@ -71,7 +71,7 @@
* priorities to fewer hardware queues (typically all to one
* hardware queue).
*/
-struct ath_txq {
+struct ath5k_txq {
unsigned int qnum; /* hardware q number */
u32 *link; /* link ptr in last TX desc */
struct list_head q; /* transmit queue */
@@ -87,7 +87,7 @@
/* Software Carrier, keeps track of the driver state
* associated with an instance of a device */
-struct ath_softc {
+struct ath5k_softc {
struct pci_dev *pdev; /* for dma mapping */
void __iomem *iobase; /* address of the device */
struct mutex lock; /* dev-level lock */
@@ -98,12 +98,12 @@
struct ieee80211_channel channels[ATH_CHAN_MAX];
struct ieee80211_rate rates[AR5K_MAX_RATES * NUM_DRIVER_MODES];
enum ieee80211_if_types opmode;
- struct ath_hw *ah; /* Atheros HW */
+ struct ath5k_hw *ah; /* Atheros HW */
int debug;
- struct ath_buf *bufptr; /* allocated buffer ptr */
- struct ath_desc *desc; /* TX/RX descriptors */
+ struct ath5k_buf *bufptr; /* allocated buffer ptr */
+ struct ath5k_desc *desc; /* TX/RX descriptors */
dma_addr_t desc_daddr; /* DMA (physical) address */
size_t desc_len; /* size of TX/RX descriptors */
u16 cachelsz; /* cache line size */
@@ -153,13 +153,13 @@
struct list_head txbuf; /* transmit buffer */
spinlock_t txbuflock;
unsigned int txbuf_len; /* buf count in txbuf list */
- struct ath_txq txqs[2]; /* beacon and tx */
+ struct ath5k_txq txqs[2]; /* beacon and tx */
- struct ath_txq *txq; /* beacon and tx*/
+ struct ath5k_txq *txq; /* beacon and tx*/
struct tasklet_struct txtq; /* tx intr tasklet */
- struct ath_buf *bbuf; /* beacon buffer */
- unsigned int bhalq, /* HAL q for outgoing beacons */
+ struct ath5k_buf *bbuf; /* beacon buffer */
+ unsigned int bhalq, /* SW q for outgoing beacons */
bmisscount, /* missed beacon transmits */
bintval, /* beacon interval */
bsent;
Modified: ath5k/trunk/hw.c
===================================================================
--- ath5k/trunk/hw.c 2007-10-29 05:07:38 UTC (rev 2796)
+++ ath5k/trunk/hw.c 2007-10-29 20:13:46 UTC (rev 2797)
@@ -21,7 +21,7 @@
*/
/*
- * HAL interface for Atheros Wireless LAN devices.
+ * HW related functions for Atheros Wireless LAN devices.
*/
#include <linux/pci.h>
@@ -38,34 +38,34 @@
static const struct ath5k_rate_table ath5k_rt_xr = AR5K_RATES_XR;
/*Prototypes*/
-static int ath5k_hw_nic_reset(struct ath_hw *, u32);
-static int ath5k_hw_nic_wakeup(struct ath_hw *, int, bool);
-static int ath5k_hw_setup_4word_tx_desc(struct ath_hw *, struct ath_desc *,
+static int ath5k_hw_nic_reset(struct ath5k_hw *, u32);
+static int ath5k_hw_nic_wakeup(struct ath5k_hw *, int, bool);
+static int ath5k_hw_setup_4word_tx_desc(struct ath5k_hw *, struct ath5k_desc *,
unsigned int, unsigned int, enum ath5k_pkt_type, unsigned int,
unsigned int, unsigned int, unsigned int, unsigned int, unsigned int,
unsigned int, unsigned int);
-static bool ath5k_hw_setup_xr_tx_desc(struct ath_hw *, struct ath_desc *,
+static bool ath5k_hw_setup_xr_tx_desc(struct ath5k_hw *, struct ath5k_desc *,
unsigned int, unsigned int, unsigned int, unsigned int, unsigned int,
unsigned int);
-static int ath5k_hw_fill_4word_tx_desc(struct ath_hw *, struct ath_desc *,
+static int ath5k_hw_fill_4word_tx_desc(struct ath5k_hw *, struct ath5k_desc *,
unsigned int, bool, bool);
-static int ath5k_hw_proc_4word_tx_status(struct ath_hw *, struct ath_desc *);
-static int ath5k_hw_setup_2word_tx_desc(struct ath_hw *, struct ath_desc *,
+static int ath5k_hw_proc_4word_tx_status(struct ath5k_hw *, struct ath5k_desc
*);
+static int ath5k_hw_setup_2word_tx_desc(struct ath5k_hw *, struct ath5k_desc *,
unsigned int, unsigned int, enum ath5k_pkt_type, unsigned int,
unsigned int, unsigned int, unsigned int, unsigned int, unsigned int,
unsigned int, unsigned int);
-static int ath5k_hw_fill_2word_tx_desc(struct ath_hw *, struct ath_desc *,
+static int ath5k_hw_fill_2word_tx_desc(struct ath5k_hw *, struct ath5k_desc *,
unsigned int, bool, bool);
-static int ath5k_hw_proc_2word_tx_status(struct ath_hw *, struct ath_desc *);
-static int ath5k_hw_proc_new_rx_status(struct ath_hw *, struct ath_desc *);
-static int ath5k_hw_proc_old_rx_status(struct ath_hw *, struct ath_desc *);
-static int ath5k_hw_get_capabilities(struct ath_hw *);
+static int ath5k_hw_proc_2word_tx_status(struct ath5k_hw *, struct ath5k_desc
*);
+static int ath5k_hw_proc_new_rx_status(struct ath5k_hw *, struct ath5k_desc *);
+static int ath5k_hw_proc_old_rx_status(struct ath5k_hw *, struct ath5k_desc *);
+static int ath5k_hw_get_capabilities(struct ath5k_hw *);
-static int ath5k_eeprom_init(struct ath_hw *);
-static int ath5k_eeprom_read_mac(struct ath_hw *, u8 *);
+static int ath5k_eeprom_init(struct ath5k_hw *);
+static int ath5k_eeprom_read_mac(struct ath5k_hw *, u8 *);
-static int ath5k_hw_enable_pspoll(struct ath_hw *, u8 *, u16);
-static int ath5k_hw_disable_pspoll(struct ath_hw *);
+static int ath5k_hw_enable_pspoll(struct ath5k_hw *, u8 *, u16);
+static int ath5k_hw_disable_pspoll(struct ath5k_hw *);
/*
* Enable to overwrite the country code (use "00" for debug)
@@ -84,7 +84,7 @@
* TODO: Left here for combatibility, change it in ath5k
*/
static u16 /*TODO: Is this really hardware dependent ?*/
-ath_hal_computetxtime(struct ath_hw *hal, const struct ath5k_rate_table *rates,
+ath5k_computetxtime(struct ath5k_hw *ah, const struct ath5k_rate_table *rates,
u32 frame_length, u16 rate_index, bool short_preamble)
{
const struct ath5k_rate *rate;
@@ -165,14 +165,14 @@
/*
* Check if a register write has been completed
*/
-int ath5k_hw_register_timeout(struct ath_hw *hal, u32 reg, u32 flag, u32 val,
+int ath5k_hw_register_timeout(struct ath5k_hw *ah, u32 reg, u32 flag, u32 val,
bool is_set)
{
int i;
u32 data;
for (i = AR5K_TUNE_REGISTER_TIMEOUT; i > 0; i--) {
- data = ath5k_hw_reg_read(hal, reg);
+ data = ath5k_hw_reg_read(ah, reg);
if ((is_set == true) && (data & flag))
break;
else if ((data & flag) == val)
@@ -191,43 +191,43 @@
/*
* Check if the device is supported and initialize the needed structs
*/
-struct ath_hw *ath5k_hw_attach(u16 device, u8 mac_version, void *sc,
+struct ath5k_hw *ath5k_hw_attach(u16 device, u8 mac_version, void *sc,
void __iomem *sh)
{
- struct ath_hw *hal;
+ struct ath5k_hw *ah;
u8 mac[ETH_ALEN];
int ret;
u32 srev;
- /*If we passed the test malloc a hal struct*/
- hal = kzalloc(sizeof(struct ath_hw), GFP_KERNEL);
- if (hal == NULL) {
+ /*If we passed the test malloc a ath5k_hw struct*/
+ ah = kzalloc(sizeof(struct ath5k_hw), GFP_KERNEL);
+ if (ah == NULL) {
ret = -ENOMEM;
AR5K_PRINT("out of memory\n");
goto err;
}
- hal->ah_sc = sc;
- hal->ah_sh = sh;
+ ah->ah_sc = sc;
+ ah->ah_sh = sh;
/*
- * HAL information
+ * HW information
*/
/* Get reg domain from eeprom */
- ath5k_get_regdomain(hal);
+ ath5k_get_regdomain(ah);
- hal->ah_op_mode = IEEE80211_IF_TYPE_STA;
- hal->ah_radar.r_enabled = AR5K_TUNE_RADAR_ALERT;
- hal->ah_turbo = false;
- hal->ah_txpower.txp_tpc = AR5K_TUNE_TPC_TXPOWER;
- hal->ah_imr = 0;
- hal->ah_atim_window = 0;
- hal->ah_aifs = AR5K_TUNE_AIFS;
- hal->ah_cw_min = AR5K_TUNE_CWMIN;
- hal->ah_limit_tx_retries = AR5K_INIT_TX_RETRY;
- hal->ah_software_retry = false;
- hal->ah_ant_diversity = AR5K_TUNE_ANT_DIVERSITY;
+ ah->ah_op_mode = IEEE80211_IF_TYPE_STA;
+ ah->ah_radar.r_enabled = AR5K_TUNE_RADAR_ALERT;
+ ah->ah_turbo = false;
+ ah->ah_txpower.txp_tpc = AR5K_TUNE_TPC_TXPOWER;
+ ah->ah_imr = 0;
+ ah->ah_atim_window = 0;
+ ah->ah_aifs = AR5K_TUNE_AIFS;
+ ah->ah_cw_min = AR5K_TUNE_CWMIN;
+ ah->ah_limit_tx_retries = AR5K_INIT_TX_RETRY;
+ ah->ah_software_retry = false;
+ ah->ah_ant_diversity = AR5K_TUNE_ANT_DIVERSITY;
switch (device) {
case PCI_DEVICE_ID_ATHEROS_AR2413:
@@ -236,94 +236,94 @@
/*
* Known single chip solutions
*/
- hal->ah_single_chip = true;
+ ah->ah_single_chip = true;
break;
default:
/*
* Multi chip solutions
*/
- hal->ah_single_chip = false;
+ ah->ah_single_chip = false;
break;
}
/*
* Set the mac revision based on the pci id
*/
- hal->ah_version = mac_version;
+ ah->ah_version = mac_version;
- /*Fill the hal struct with the needed functions*/
- if (hal->ah_version == AR5K_AR5212)
- hal->ah_magic = AR5K_EEPROM_MAGIC_5212;
- else if (hal->ah_version == AR5K_AR5211)
- hal->ah_magic = AR5K_EEPROM_MAGIC_5211;
+ /*Fill the ath5k_hw struct with the needed functions*/
+ if (ah->ah_version == AR5K_AR5212)
+ ah->ah_magic = AR5K_EEPROM_MAGIC_5212;
+ else if (ah->ah_version == AR5K_AR5211)
+ ah->ah_magic = AR5K_EEPROM_MAGIC_5211;
- if (hal->ah_version == AR5K_AR5212) {
- hal->ah_setup_tx_desc = ath5k_hw_setup_4word_tx_desc;
- hal->ah_setup_xtx_desc = ath5k_hw_setup_xr_tx_desc;
- hal->ah_fill_tx_desc = ath5k_hw_fill_4word_tx_desc;
- hal->ah_proc_tx_desc = ath5k_hw_proc_4word_tx_status;
+ if (ah->ah_version == AR5K_AR5212) {
+ ah->ah_setup_tx_desc = ath5k_hw_setup_4word_tx_desc;
+ ah->ah_setup_xtx_desc = ath5k_hw_setup_xr_tx_desc;
+ ah->ah_fill_tx_desc = ath5k_hw_fill_4word_tx_desc;
+ ah->ah_proc_tx_desc = ath5k_hw_proc_4word_tx_status;
} else {
- hal->ah_setup_tx_desc = ath5k_hw_setup_2word_tx_desc;
- hal->ah_setup_xtx_desc = ath5k_hw_setup_xr_tx_desc;
- hal->ah_fill_tx_desc = ath5k_hw_fill_2word_tx_desc;
- hal->ah_proc_tx_desc = ath5k_hw_proc_2word_tx_status;
+ ah->ah_setup_tx_desc = ath5k_hw_setup_2word_tx_desc;
+ ah->ah_setup_xtx_desc = ath5k_hw_setup_xr_tx_desc;
+ ah->ah_fill_tx_desc = ath5k_hw_fill_2word_tx_desc;
+ ah->ah_proc_tx_desc = ath5k_hw_proc_2word_tx_status;
}
- if (hal->ah_version == AR5K_AR5212)
- hal->ah_proc_rx_desc = ath5k_hw_proc_new_rx_status;
- else if (hal->ah_version <= AR5K_AR5211)
- hal->ah_proc_rx_desc = ath5k_hw_proc_old_rx_status;
+ if (ah->ah_version == AR5K_AR5212)
+ ah->ah_proc_rx_desc = ath5k_hw_proc_new_rx_status;
+ else if (ah->ah_version <= AR5K_AR5211)
+ ah->ah_proc_rx_desc = ath5k_hw_proc_old_rx_status;
/* Bring device out of sleep and reset it's units */
- ret = ath5k_hw_nic_wakeup(hal, AR5K_INIT_MODE, true);
+ ret = ath5k_hw_nic_wakeup(ah, AR5K_INIT_MODE, true);
if (ret)
goto err_free;
/* Get MAC, PHY and RADIO revisions */
- srev = ath5k_hw_reg_read(hal, AR5K_SREV);
- hal->ah_mac_srev = srev;
- hal->ah_mac_version = AR5K_REG_MS(srev, AR5K_SREV_VER);
- hal->ah_mac_revision = AR5K_REG_MS(srev, AR5K_SREV_REV);
- hal->ah_phy_revision = ath5k_hw_reg_read(hal, AR5K_PHY_CHIP_ID) &
+ srev = ath5k_hw_reg_read(ah, AR5K_SREV);
+ ah->ah_mac_srev = srev;
+ ah->ah_mac_version = AR5K_REG_MS(srev, AR5K_SREV_VER);
+ ah->ah_mac_revision = AR5K_REG_MS(srev, AR5K_SREV_REV);
+ ah->ah_phy_revision = ath5k_hw_reg_read(ah, AR5K_PHY_CHIP_ID) &
0xffffffff;
- hal->ah_radio_5ghz_revision = ath5k_hw_radio_revision(hal,
+ ah->ah_radio_5ghz_revision = ath5k_hw_radio_revision(ah,
CHANNEL_5GHZ);
- if (hal->ah_version == AR5K_AR5210)
- hal->ah_radio_2ghz_revision = 0;
+ if (ah->ah_version == AR5K_AR5210)
+ ah->ah_radio_2ghz_revision = 0;
else
- hal->ah_radio_2ghz_revision = ath5k_hw_radio_revision(hal,
+ ah->ah_radio_2ghz_revision = ath5k_hw_radio_revision(ah,
CHANNEL_2GHZ);
/* Single chip radio */
- if (hal->ah_radio_2ghz_revision == hal->ah_radio_5ghz_revision)
- hal->ah_radio_2ghz_revision = 0;
+ if (ah->ah_radio_2ghz_revision == ah->ah_radio_5ghz_revision)
+ ah->ah_radio_2ghz_revision = 0;
/* Identify the radio chip*/
- if (hal->ah_version == AR5K_AR5210)
- hal->ah_radio = AR5K_RF5110;
+ if (ah->ah_version == AR5K_AR5210)
+ ah->ah_radio = AR5K_RF5110;
else
- hal->ah_radio = hal->ah_radio_5ghz_revision <
+ ah->ah_radio = ah->ah_radio_5ghz_revision <
AR5K_SREV_RAD_5112 ? AR5K_RF5111 : AR5K_RF5112;
- hal->ah_phy = AR5K_PHY(0);
+ ah->ah_phy = AR5K_PHY(0);
#ifdef AR5K_DEBUG
- ath5k_hw_dump_state(hal);
+ ath5k_hw_dump_state(ah);
#endif
/*
* Get card capabilities, values, ...
*/
- ret = ath5k_eeprom_init(hal);
+ ret = ath5k_eeprom_init(ah);
if (ret) {
AR5K_PRINT("unable to init EEPROM\n");
goto err_free;
}
/* Get misc capabilities */
- ret = ath5k_hw_get_capabilities(hal);
+ ret = ath5k_hw_get_capabilities(ah);
if (ret) {
AR5K_PRINTF("unable to get device capabilities: 0x%04x\n",
device);
@@ -331,24 +331,24 @@
}
/* Get MAC address */
- ret = ath5k_eeprom_read_mac(hal, mac);
+ ret = ath5k_eeprom_read_mac(ah, mac);
if (ret) {
AR5K_PRINTF("unable to read address from EEPROM: 0x%04x\n",
device);
goto err_free;
}
- ath5k_hw_set_lladdr(hal, mac);
+ ath5k_hw_set_lladdr(ah, mac);
/* Set BSSID to bcast address: ff:ff:ff:ff:ff:ff for now */
- memset(hal->bssid, 0xff, ETH_ALEN);
- ath5k_hw_set_associd(hal, hal->bssid, 0);
- ath5k_hw_set_opmode(hal);
+ memset(ah->bssid, 0xff, ETH_ALEN);
+ ath5k_hw_set_associd(ah, ah->bssid, 0);
+ ath5k_hw_set_opmode(ah);
- ath5k_hw_set_rfgain_opt(hal);
+ ath5k_hw_set_rfgain_opt(ah);
- return hal;
+ return ah;
err_free:
- kfree(hal);
+ kfree(ah);
err:
return ERR_PTR(ret);
}
@@ -356,7 +356,7 @@
/*
* Bring up MAC + PHY Chips
*/
-static int ath5k_hw_nic_wakeup(struct ath_hw *hal, int flags, bool initial)
+static int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, int flags, bool initial)
{
u32 turbo, mode, clock;
int ret;
@@ -367,12 +367,12 @@
AR5K_TRACE;
- if (hal->ah_version != AR5K_AR5210) {
+ if (ah->ah_version != AR5K_AR5210) {
/*
* Get channel mode flags
*/
- if (hal->ah_radio >= AR5K_RF5112) {
+ if (ah->ah_radio >= AR5K_RF5112) {
mode = AR5K_PHY_MODE_RAD_RF5112;
clock = AR5K_PHY_PLL_RF5112;
} else {
@@ -393,7 +393,7 @@
* this, 5211 might support ofdm-only g after
* all, there are also initial register values
* in the code for g mode (see ath5k_hw.h). */
- if (hal->ah_version == AR5K_AR5211)
+ if (ah->ah_version == AR5K_AR5211)
mode |= AR5K_PHY_MODE_MOD_OFDM;
else
mode |= AR5K_PHY_MODE_MOD_DYN;
@@ -421,7 +421,7 @@
} else { /* Reset and wakeup the device */
if (initial == true) {
/* ...reset hardware */
- if (ath5k_hw_nic_reset(hal, AR5K_RESET_CTL_PCI)) {
+ if (ath5k_hw_nic_reset(ah, AR5K_RESET_CTL_PCI)) {
AR5K_PRINT("failed to reset the PCI chipset\n");
return -EIO;
}
@@ -430,7 +430,7 @@
}
/* ...wakeup */
- ret = ath5k_hw_set_power(hal, AR5K_PM_AWAKE, true, 0);
+ ret = ath5k_hw_set_power(ah, AR5K_PM_AWAKE, true, 0);
if (ret) {
AR5K_PRINT("failed to resume the MAC Chip\n");
return ret;
@@ -438,11 +438,11 @@
/* ...enable Atheros turbo mode if requested */
if (flags & CHANNEL_TURBO)
- ath5k_hw_reg_write(hal, AR5K_PHY_TURBO_MODE,
+ ath5k_hw_reg_write(ah, AR5K_PHY_TURBO_MODE,
AR5K_PHY_TURBO);
/* ...reset chipset */
- if (ath5k_hw_nic_reset(hal, AR5K_RESET_CTL_CHIP)) {
+ if (ath5k_hw_nic_reset(ah, AR5K_RESET_CTL_CHIP)) {
AR5K_PRINT("failed to reset the AR5210 chipset\n");
return -EIO;
}
@@ -451,35 +451,35 @@
}
/* ...reset chipset and PCI device */
- if (hal->ah_single_chip == false && ath5k_hw_nic_reset(hal,
+ if (ah->ah_single_chip == false && ath5k_hw_nic_reset(ah,
AR5K_RESET_CTL_CHIP | AR5K_RESET_CTL_PCI)) {
AR5K_PRINT("failed to reset the MAC Chip + PCI\n");
return -EIO;
}
- if (hal->ah_version == AR5K_AR5210)
+ if (ah->ah_version == AR5K_AR5210)
udelay(2300);
/* ...wakeup */
- ret = ath5k_hw_set_power(hal, AR5K_PM_AWAKE, true, 0);
+ ret = ath5k_hw_set_power(ah, AR5K_PM_AWAKE, true, 0);
if (ret) {
AR5K_PRINT("failed to resume the MAC Chip\n");
return ret;
}
/* ...final warm reset */
- if (ath5k_hw_nic_reset(hal, 0)) {
+ if (ath5k_hw_nic_reset(ah, 0)) {
AR5K_PRINT("failed to warm reset the MAC Chip\n");
return -EIO;
}
- if (hal->ah_version != AR5K_AR5210) {
+ if (ah->ah_version != AR5K_AR5210) {
/* ...set the PHY operating mode */
- ath5k_hw_reg_write(hal, clock, AR5K_PHY_PLL);
+ ath5k_hw_reg_write(ah, clock, AR5K_PHY_PLL);
udelay(300);
- ath5k_hw_reg_write(hal, mode, AR5K_PHY_MODE);
- ath5k_hw_reg_write(hal, turbo, AR5K_PHY_TURBO);
+ ath5k_hw_reg_write(ah, mode, AR5K_PHY_MODE);
+ ath5k_hw_reg_write(ah, turbo, AR5K_PHY_TURBO);
}
return 0;
@@ -488,12 +488,12 @@
/*
* Get the rate table for a specific operation mode
*/
-const struct ath5k_rate_table *ath5k_hw_get_rate_table(struct ath_hw *hal,
+const struct ath5k_rate_table *ath5k_hw_get_rate_table(struct ath5k_hw *ah,
unsigned int mode)
{
AR5K_TRACE;
- if (!test_bit(mode, hal->ah_capabilities.cap_mode))
+ if (!test_bit(mode, ah->ah_capabilities.cap_mode))
return NULL;
/* Get rate tables */
@@ -514,17 +514,17 @@
}
/*
- * Free the hal struct
+ * Free the ath5k_hw struct
*/
-void ath5k_hw_detach(struct ath_hw *hal)
+void ath5k_hw_detach(struct ath5k_hw *ah)
{
AR5K_TRACE;
- if (hal->ah_rf_banks != NULL)
- kfree(hal->ah_rf_banks);
+ if (ah->ah_rf_banks != NULL)
+ kfree(ah->ah_rf_banks);
/* assume interrupts are down */
- kfree(hal);
+ kfree(ah);
}
/*******************************\
@@ -534,12 +534,13 @@
/*
* Main reset function
*/
-int ath5k_hw_reset(struct ath_hw *hal, enum ieee80211_if_types op_mode,
+int ath5k_hw_reset(struct ath5k_hw *ah, enum ieee80211_if_types op_mode,
struct ieee80211_channel *channel, bool change_channel)
{
const struct ath5k_rate_table *rt;
- struct ath5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom;
- u32 data, noise_floor, s_seq, s_ant, s_led[3];
+ struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
+ u32 data, s_seq, s_ant, s_led[3];
+ s32 noise_floor;
unsigned int i, mode, freq, ee_mode, ant[2];
int ret;
@@ -555,43 +556,43 @@
* Save some registers before a reset
*/
/*DCU/Antenna selection not available on 5210*/
- if (hal->ah_version != AR5K_AR5210) {
+ if (ah->ah_version != AR5K_AR5210) {
if (change_channel == true) {
/* Seq number for queue 0 -do this for all queues ? */
- s_seq = ath5k_hw_reg_read(hal,
+ s_seq = ath5k_hw_reg_read(ah,
AR5K_QUEUE_DFS_SEQNUM(0));
/*Default antenna*/
- s_ant = ath5k_hw_reg_read(hal, AR5K_DEFAULT_ANTENNA);
+ s_ant = ath5k_hw_reg_read(ah, AR5K_DEFAULT_ANTENNA);
}
}
/*GPIOs*/
- s_led[0] = ath5k_hw_reg_read(hal, AR5K_PCICFG) & AR5K_PCICFG_LEDSTATE;
- s_led[1] = ath5k_hw_reg_read(hal, AR5K_GPIOCR);
- s_led[2] = ath5k_hw_reg_read(hal, AR5K_GPIODO);
+ s_led[0] = ath5k_hw_reg_read(ah, AR5K_PCICFG) & AR5K_PCICFG_LEDSTATE;
+ s_led[1] = ath5k_hw_reg_read(ah, AR5K_GPIOCR);
+ s_led[2] = ath5k_hw_reg_read(ah, AR5K_GPIODO);
- if (change_channel == true && hal->ah_rf_banks != NULL)
- ath5k_hw_get_rf_gain(hal);
+ if (change_channel == true && ah->ah_rf_banks != NULL)
+ ath5k_hw_get_rf_gain(ah);
/*Wakeup the device*/
- ret = ath5k_hw_nic_wakeup(hal, channel->val, false);
+ ret = ath5k_hw_nic_wakeup(ah, channel->val, false);
if (ret)
return ret;
/*
* Initialize operating mode
*/
- hal->ah_op_mode = op_mode;
+ ah->ah_op_mode = op_mode;
/*
* 5111/5112 Settings
* 5210 only comes with RF5110
*/
- if (hal->ah_version != AR5K_AR5210) {
- if (hal->ah_radio != AR5K_RF5111 &&
- hal->ah_radio != AR5K_RF5112) {
- AR5K_PRINTF("invalid phy radio: %u\n", hal->ah_radio);
+ if (ah->ah_version != AR5K_AR5210) {
+ if (ah->ah_radio != AR5K_RF5111 &&
+ ah->ah_radio != AR5K_RF5112) {
+ AR5K_PRINTF("invalid phy radio: %u\n", ah->ah_radio);
return -EINVAL;
}
@@ -624,7 +625,7 @@
ee_mode = AR5K_EEPROM_MODE_11G;
break;
case CHANNEL_XR:
- if (hal->ah_version == AR5K_AR5211) {
+ if (ah->ah_version == AR5K_AR5211) {
AR5K_PRINTF("XR mode not available on 5211");
return -EINVAL;
}
@@ -638,21 +639,21 @@
}
/* PHY access enable */
- ath5k_hw_reg_write(hal, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0));
+ ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0));
}
- ath5k_hw_write_initvals(hal, mode, change_channel);
+ ath5k_hw_write_initvals(ah, mode, change_channel);
/*
* 5211/5212 Specific
*/
- if (hal->ah_version != AR5K_AR5210) {
+ if (ah->ah_version != AR5K_AR5210) {
/*
* Write initial RF gain settings
* This should work for both 5111/5112
*/
- ret = ath5k_hw_rfgain(hal, freq);
+ ret = ath5k_hw_rfgain(ah, freq);
if (ret)
return ret;
@@ -661,13 +662,13 @@
/*
* Set rate duration table on 5212
*/
- if (hal->ah_version == AR5K_AR5212) {
+ if (ah->ah_version == AR5K_AR5212) {
/*For 802.11b*/
if (!(channel->val & CHANNEL_B)) {
/*Get rate table for this operation mode*/
- rt = ath5k_hw_get_rate_table(hal,
+ rt = ath5k_hw_get_rate_table(ah,
MODE_IEEE80211B);
if (!rt)
return -EINVAL;
@@ -675,13 +676,13 @@
/*Write rate duration table*/
for (i = 0; i < rt->rate_count; i++) {
data =
AR5K_RATE_DUR(rt->rates[i].rate_code);
- ath5k_hw_reg_write(hal,
- ath_hal_computetxtime(hal, rt,
+ ath5k_hw_reg_write(ah,
+ ath5k_computetxtime(ah, rt,
14, rt->rates[i].control_rate,
false), data);
if (HAS_SHPREAMBLE(i))
- ath5k_hw_reg_write(hal,
- ath_hal_computetxtime(hal,
+ ath5k_hw_reg_write(ah,
+ ath5k_computetxtime(ah,
rt, 14,
rt->rates[i].control_rate,
false), data +
@@ -693,7 +694,7 @@
* O.K. for both a/g - OFDM) */
/* Get rate table for this operation mode */
- rt = ath5k_hw_get_rate_table(hal,
+ rt = ath5k_hw_get_rate_table(ah,
channel->val & CHANNEL_TURBO ?
MODE_ATHEROS_TURBO : MODE_ATHEROS_TURBOG);
if (!rt)
@@ -701,8 +702,8 @@
/* Write rate duration table */
for (i = 0; i < rt->rate_count; i++)
- ath5k_hw_reg_write(hal,
- ath_hal_computetxtime(hal, rt,
+ ath5k_hw_reg_write(ah,
+ ath5k_computetxtime(ah, rt,
14, rt->rates[i].control_rate,
false),
AR5K_RATE_DUR(rt->rates[i].rate_code));
@@ -711,22 +712,22 @@
}
/* Fix for first revision of the RF5112 RF chipset */
- if (hal->ah_radio >= AR5K_RF5112 &&
- hal->ah_radio_5ghz_revision <
+ if (ah->ah_radio >= AR5K_RF5112 &&
+ ah->ah_radio_5ghz_revision <
AR5K_SREV_RAD_5112A) {
- ath5k_hw_reg_write(hal, AR5K_PHY_CCKTXCTL_WORLD,
+ ath5k_hw_reg_write(ah, AR5K_PHY_CCKTXCTL_WORLD,
AR5K_PHY_CCKTXCTL);
if (channel->val & CHANNEL_A)
data = 0xffb81020;
else
data = 0xffb80d20;
- ath5k_hw_reg_write(hal, data, AR5K_PHY_FRAME_CTL);
+ ath5k_hw_reg_write(ah, data, AR5K_PHY_FRAME_CTL);
}
/*
* Set TX power (XXX use txpower from net80211)
*/
- ret = ath5k_hw_txpower(hal, channel, AR5K_TUNE_DEFAULT_TXPOWER);
+ ret = ath5k_hw_txpower(ah, channel, AR5K_TUNE_DEFAULT_TXPOWER);
if (ret)
return ret;
@@ -734,7 +735,7 @@
* Write RF registers
* TODO:Does this work on 5211 (5111) ?
*/
- ret = ath5k_hw_rfregs(hal, channel, mode);
+ ret = ath5k_hw_rfregs(ah, channel, mode);
if (ret)
return ret;
@@ -743,7 +744,7 @@
*/
/* Write OFDM timings on 5212*/
- if (hal->ah_version == AR5K_AR5212) {
+ if (ah->ah_version == AR5K_AR5212) {
if (channel->val & CHANNEL_OFDM) {
u32 coef_scaled, coef_exp, coef_man,
ds_coef_exp, ds_coef_man, clock;
@@ -765,84 +766,84 @@
ds_coef_man = coef_man >> (24 - coef_exp);
ds_coef_exp = coef_exp - 16;
- AR5K_REG_WRITE_BITS(hal, AR5K_PHY_TIMING_3,
+ AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_3,
AR5K_PHY_TIMING_3_DSC_MAN, ds_coef_man);
- AR5K_REG_WRITE_BITS(hal, AR5K_PHY_TIMING_3,
+ AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_3,
AR5K_PHY_TIMING_3_DSC_EXP, ds_coef_exp);
}
}
/*Enable/disable 802.11b mode on 5111
(enable 2111 frequency converter + CCK)*/
- if (hal->ah_radio == AR5K_RF5111) {
+ if (ah->ah_radio == AR5K_RF5111) {
if (channel->val & CHANNEL_B)
- AR5K_REG_ENABLE_BITS(hal, AR5K_TXCFG,
+ AR5K_REG_ENABLE_BITS(ah, AR5K_TXCFG,
AR5K_TXCFG_B_MODE);
else
- AR5K_REG_DISABLE_BITS(hal, AR5K_TXCFG,
+ AR5K_REG_DISABLE_BITS(ah, AR5K_TXCFG,
AR5K_TXCFG_B_MODE);
}
/* Set antenna mode */
- AR5K_REG_MASKED_BITS(hal, AR5K_PHY(0x44),
- hal->ah_antenna[ee_mode][0], 0xfffffc06);
+ AR5K_REG_MASKED_BITS(ah, AR5K_PHY(0x44),
+ ah->ah_antenna[ee_mode][0], 0xfffffc06);
if (freq == AR5K_INI_RFGAIN_2GHZ)
ant[0] = ant[1] = AR5K_ANT_FIXED_B;
else
ant[0] = ant[1] = AR5K_ANT_FIXED_A;
- ath5k_hw_reg_write(hal, hal->ah_antenna[ee_mode][ant[0]],
+ ath5k_hw_reg_write(ah, ah->ah_antenna[ee_mode][ant[0]],
AR5K_PHY_ANT_SWITCH_TABLE_0);
- ath5k_hw_reg_write(hal, hal->ah_antenna[ee_mode][ant[1]],
+ ath5k_hw_reg_write(ah, ah->ah_antenna[ee_mode][ant[1]],
AR5K_PHY_ANT_SWITCH_TABLE_1);
/* Commit values from EEPROM */
- if (hal->ah_radio == AR5K_RF5111)
- AR5K_REG_WRITE_BITS(hal, AR5K_PHY_FRAME_CTL,
+ if (ah->ah_radio == AR5K_RF5111)
+ AR5K_REG_WRITE_BITS(ah, AR5K_PHY_FRAME_CTL,
AR5K_PHY_FRAME_CTL_TX_CLIP, ee->ee_tx_clip);
- ath5k_hw_reg_write(hal,
+ ath5k_hw_reg_write(ah,
AR5K_PHY_NF_SVAL(ee->ee_noise_floor_thr[ee_mode]),
AR5K_PHY(0x5a));
- AR5K_REG_MASKED_BITS(hal, AR5K_PHY(0x11),
+ AR5K_REG_MASKED_BITS(ah, AR5K_PHY(0x11),
(ee->ee_switch_settling[ee_mode] << 7) & 0x3f80,
0xffffc07f);
- AR5K_REG_MASKED_BITS(hal, AR5K_PHY(0x12),
+ AR5K_REG_MASKED_BITS(ah, AR5K_PHY(0x12),
(ee->ee_ant_tx_rx[ee_mode] << 12) & 0x3f000,
0xfffc0fff);
- AR5K_REG_MASKED_BITS(hal, AR5K_PHY(0x14),
+ AR5K_REG_MASKED_BITS(ah, AR5K_PHY(0x14),
(ee->ee_adc_desired_size[ee_mode] & 0x00ff) |
((ee->ee_pga_desired_size[ee_mode] << 8) & 0xff00),
0xffff0000);
- ath5k_hw_reg_write(hal,
+ ath5k_hw_reg_write(ah,
(ee->ee_tx_end2xpa_disable[ee_mode] << 24) |
(ee->ee_tx_end2xpa_disable[ee_mode] << 16) |
(ee->ee_tx_frm2xpa_enable[ee_mode] << 8) |
(ee->ee_tx_frm2xpa_enable[ee_mode]), AR5K_PHY(0x0d));
- AR5K_REG_MASKED_BITS(hal, AR5K_PHY(0x0a),
+ AR5K_REG_MASKED_BITS(ah, AR5K_PHY(0x0a),
ee->ee_tx_end2xlna_enable[ee_mode] << 8, 0xffff00ff);
- AR5K_REG_MASKED_BITS(hal, AR5K_PHY(0x19),
+ AR5K_REG_MASKED_BITS(ah, AR5K_PHY(0x19),
(ee->ee_thr_62[ee_mode] << 12) & 0x7f000, 0xfff80fff);
- AR5K_REG_MASKED_BITS(hal, AR5K_PHY(0x49), 4, 0xffffff01);
+ AR5K_REG_MASKED_BITS(ah, AR5K_PHY(0x49), 4, 0xffffff01);
- AR5K_REG_ENABLE_BITS(hal, AR5K_PHY_IQ,
+ AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ,
AR5K_PHY_IQ_CORR_ENABLE |
(ee->ee_i_cal[ee_mode] << AR5K_PHY_IQ_CORR_Q_I_COFF_S) |
ee->ee_q_cal[ee_mode]);
- if (hal->ah_ee_version >= AR5K_EEPROM_VERSION_4_1)
- AR5K_REG_WRITE_BITS(hal, AR5K_PHY_GAIN_2GHZ,
+ if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_1)
+ AR5K_REG_WRITE_BITS(ah, AR5K_PHY_GAIN_2GHZ,
AR5K_PHY_GAIN_2GHZ_MARGIN_TXRX,
ee->ee_margin_tx_rx[ee_mode]);
} else {
mdelay(1);
/* Disable phy and wait */
- ath5k_hw_reg_write(hal, AR5K_PHY_ACT_DISABLE, AR5K_PHY_ACT);
+ ath5k_hw_reg_write(ah, AR5K_PHY_ACT_DISABLE, AR5K_PHY_ACT);
mdelay(1);
}
@@ -850,61 +851,61 @@
* Restore saved values
*/
/*DCU/Antenna selection not available on 5210*/
- if (hal->ah_version != AR5K_AR5210) {
- ath5k_hw_reg_write(hal, s_seq, AR5K_QUEUE_DFS_SEQNUM(0));
- ath5k_hw_reg_write(hal, s_ant, AR5K_DEFAULT_ANTENNA);
+ if (ah->ah_version != AR5K_AR5210) {
+ ath5k_hw_reg_write(ah, s_seq, AR5K_QUEUE_DFS_SEQNUM(0));
+ ath5k_hw_reg_write(ah, s_ant, AR5K_DEFAULT_ANTENNA);
}
- AR5K_REG_ENABLE_BITS(hal, AR5K_PCICFG, s_led[0]);
- ath5k_hw_reg_write(hal, s_led[1], AR5K_GPIOCR);
- ath5k_hw_reg_write(hal, s_led[2], AR5K_GPIODO);
+ AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG, s_led[0]);
+ ath5k_hw_reg_write(ah, s_led[1], AR5K_GPIOCR);
+ ath5k_hw_reg_write(ah, s_led[2], AR5K_GPIODO);
/*
* Misc
*/
- /* XXX: add hal->aid once mac80211 gives this to us */
- ath5k_hw_set_associd(hal, hal->bssid, 0);
+ /* XXX: add ah->aid once mac80211 gives this to us */
+ ath5k_hw_set_associd(ah, ah->bssid, 0);
- ath5k_hw_set_opmode(hal);
+ ath5k_hw_set_opmode(ah);
/*PISR/SISR Not available on 5210*/
- if (hal->ah_version != AR5K_AR5210) {
- ath5k_hw_reg_write(hal, 0xffffffff, AR5K_PISR);
+ if (ah->ah_version != AR5K_AR5210) {
+ ath5k_hw_reg_write(ah, 0xffffffff, AR5K_PISR);
/* XXX: AR5K_RSSI_THR has masks and shifts defined for it, so
* direct write using ath5k_hw_reg_write seems wrong. Test with:
- * AR5K_REG_WRITE_BITS(hal, AR5K_RSSI_THR,
+ * AR5K_REG_WRITE_BITS(ah, AR5K_RSSI_THR,
* AR5K_RSSI_THR_BMISS, AR5K_TUNE_RSSI_THRES);
* with different variables and check results compared
- * to ath5k_hw_reg_write(hal, ) */
- ath5k_hw_reg_write(hal, AR5K_TUNE_RSSI_THRES, AR5K_RSSI_THR);
+ * to ath5k_hw_reg_write(ah, ) */
+ ath5k_hw_reg_write(ah, AR5K_TUNE_RSSI_THRES, AR5K_RSSI_THR);
}
/*
* Set Rx/Tx DMA Configuration
*(passing dma size not available on 5210)
*/
- if (hal->ah_version != AR5K_AR5210) {
- AR5K_REG_WRITE_BITS(hal, AR5K_TXCFG, AR5K_TXCFG_SDMAMR,
+ if (ah->ah_version != AR5K_AR5210) {
+ AR5K_REG_WRITE_BITS(ah, AR5K_TXCFG, AR5K_TXCFG_SDMAMR,
AR5K_DMASIZE_512B | AR5K_TXCFG_DMASIZE);
- AR5K_REG_WRITE_BITS(hal, AR5K_RXCFG, AR5K_RXCFG_SDMAMW,
+ AR5K_REG_WRITE_BITS(ah, AR5K_RXCFG, AR5K_RXCFG_SDMAMW,
AR5K_DMASIZE_512B);
}
/*
* Set channel and calibrate the PHY
*/
- ret = ath5k_hw_channel(hal, channel);
+ ret = ath5k_hw_channel(ah, channel);
if (ret)
return ret;
/*
* Enable the PHY and wait until completion
*/
- ath5k_hw_reg_write(hal, AR5K_PHY_ACT_ENABLE, AR5K_PHY_ACT);
+ ath5k_hw_reg_write(ah, AR5K_PHY_ACT_ENABLE, AR5K_PHY_ACT);
/*
* 5111/5112 Specific
*/
- if (hal->ah_version != AR5K_AR5210) {
- data = ath5k_hw_reg_read(hal, AR5K_PHY_RX_DELAY) &
+ if (ah->ah_version != AR5K_AR5210) {
+ data = ath5k_hw_reg_read(ah, AR5K_PHY_RX_DELAY) &
AR5K_PHY_RX_DELAY_M;
data = (channel->val & CHANNEL_CCK) ?
((data << 2) / 22) : (data / 10);
@@ -917,10 +918,10 @@
/*
* Enable calibration and wait until completion
*/
- AR5K_REG_ENABLE_BITS(hal, AR5K_PHY_AGCCTL,
+ AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL,
AR5K_PHY_AGCCTL_CAL);
- if (ath5k_hw_register_timeout(hal, AR5K_PHY_AGCCTL,
+ if (ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL,
AR5K_PHY_AGCCTL_CAL, 0, false)) {
AR5K_PRINTF("calibration timeout (%uMHz)\n", channel->freq);
return -EAGAIN;
@@ -929,10 +930,10 @@
/*
* Enable noise floor calibration and wait until completion
*/
- AR5K_REG_ENABLE_BITS(hal, AR5K_PHY_AGCCTL,
+ AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL,
AR5K_PHY_AGCCTL_NF);
- if (ath5k_hw_register_timeout(hal, AR5K_PHY_AGCCTL,
+ if (ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL,
AR5K_PHY_AGCCTL_NF, 0, false)) {
AR5K_PRINTF("noise floor calibration timeout (%uMHz)\n",
channel->freq);
@@ -942,10 +943,9 @@
/* Wait until the noise floor is calibrated and read the value */
for (i = 20; i > 0; i--) {
mdelay(1);
- noise_floor = ath5k_hw_reg_read(hal, AR5K_PHY_NF);
+ noise_floor = ath5k_hw_reg_read(ah, AR5K_PHY_NF);
- if (AR5K_PHY_NF_RVAL(noise_floor) &
- AR5K_PHY_NF_ACTIVE)
+ if (AR5K_PHY_NF_RVAL(noise_floor) & AR5K_PHY_NF_ACTIVE)
noise_floor = AR5K_PHY_NF_AVAL(noise_floor);
if (noise_floor <= AR5K_TUNE_NOISE_FLOOR)
@@ -958,25 +958,25 @@
return -EIO;
}
- hal->ah_calibration = false;
+ ah->ah_calibration = false;
if (!(channel->val & CHANNEL_B)) {
- hal->ah_calibration = true;
- AR5K_REG_WRITE_BITS(hal, AR5K_PHY_IQ,
+ ah->ah_calibration = true;
+ AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ,
AR5K_PHY_IQ_CAL_NUM_LOG_MAX, 15);
- AR5K_REG_ENABLE_BITS(hal, AR5K_PHY_IQ,
+ AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ,
AR5K_PHY_IQ_RUN);
}
/*
* Reset queues and start beacon timers at the end of the reset routine
*/
- for (i = 0; i < hal->ah_capabilities.cap_queues.q_tx_num; i++) {
+ for (i = 0; i < ah->ah_capabilities.cap_queues.q_tx_num; i++) {
/*No QCU on 5210*/
- if (hal->ah_version != AR5K_AR5210)
- AR5K_REG_WRITE_Q(hal, AR5K_QUEUE_QCUMASK(i), i);
+ if (ah->ah_version != AR5K_AR5210)
+ AR5K_REG_WRITE_Q(ah, AR5K_QUEUE_QCUMASK(i), i);
- ret = ath5k_hw_reset_tx_queue(hal, i);
+ ret = ath5k_hw_reset_tx_queue(ah, i);
if (ret) {
AR5K_PRINTF("failed to reset TX queue #%d\n", i);
return ret;
@@ -984,36 +984,36 @@
}
/* Pre-enable interrupts on 5211/5 |
