Project : madwifi
Revision : 2671
Author : mickflemm (Nick Kossifidis)
Date : 2007-08-26 18:17:52 +0200 (Sun, 26 Aug 2007)
Log Message :
* Split ath5k_hw.c on two files, one for the initial register settings and
one for the phy specific functions.
Affected Files:
* branches/ath5k/Kconfig updated
* branches/ath5k/Makefile updated
* branches/ath5k/ath5k.h updated
* branches/ath5k/ath5k_hw.c updated
* branches/ath5k/ath5k_hw.h updated
* branches/ath5k/ath5k_hw_inivals.c added
* branches/ath5k/ath5k_hw_phy.c added
* branches/ath5k/ath5k_hw_regs.h added
* branches/ath5k/ath5kreg.h deleted
Modified: branches/ath5k/Kconfig
===================================================================
--- branches/ath5k/Kconfig 2007-08-26 09:34:43 UTC (rev 2670)
+++ branches/ath5k/Kconfig 2007-08-26 16:17:52 UTC (rev 2671)
@@ -12,3 +12,18 @@
To compile this driver as a module, choose M here: the module will be
called ath5k_pci. If unsure, say N.
+config ATHEROS_AR5K_AR5210
+ bool "Support AR5210"
+ depends on ATHEROS_AR5K
+ default y
+
+config ATHEROS_AR5K_AR5211
+ bool "Support AR5211"
+ depends on ATHEROS_AR5K
+ default y
+
+config ATHEROS_AR5K_AR5212
+ bool "Support AR5212"
+ depends on ATHEROS_AR5K
+ default y
+
Modified: branches/ath5k/Makefile
===================================================================
--- branches/ath5k/Makefile 2007-08-26 09:34:43 UTC (rev 2670)
+++ branches/ath5k/Makefile 2007-08-26 16:17:52 UTC (rev 2671)
@@ -1,5 +1,5 @@
obj-m += ath5k_pci.o
-ath5k_pci-objs := ath5k.o ath5k_hw.o ieee80211_regdomain.o
+ath5k_pci-objs := ath5k.o ath5k_hw.o ath5k_hw_phy.o ath5k_hw_inivals.o
ieee80211_regdomain.o
all:
make -C /lib/modules/$(shell uname -r)/build/ M=$(PWD) modules
Modified: branches/ath5k/ath5k.h
===================================================================
--- branches/ath5k/ath5k.h 2007-08-26 09:34:43 UTC (rev 2670)
+++ branches/ath5k/ath5k.h 2007-08-26 16:17:52 UTC (rev 2671)
@@ -44,7 +44,7 @@
#include <net/mac80211.h>
/* Register addresses and values */
-#include "ath5kreg.h"
+#include "ath5k_hw_regs.h"
/* HW structures and misc defines used by hw functions */
#include "ath5k_hw.h"
@@ -1201,7 +1201,7 @@
/*
- * Prototypes - hw functions
+ * Prototypes - MAC functions
*/
/* General TODO: Clean them up */
@@ -1215,10 +1215,9 @@
extern const AR5K_RATE_TABLE* ath5k_hw_get_rate_table(struct ath_hal*, u_int
mode);
/* Attach/detach */
-struct ath_hal* ath5k_hw_init(u_int16_t device, AR5K_SOFTC sc,
AR5K_BUS_TAG,
+extern struct ath_hal* ath5k_hw_init(u_int16_t device, AR5K_SOFTC sc,
AR5K_BUS_TAG,
AR5K_BUS_HANDLE, AR5K_STATUS *);
AR5K_BOOL ath5k_hw_nic_wakeup(struct ath_hal *, u_int16_t,
AR5K_BOOL);
-u_int16_t ath5k_hw_radio_revision(struct ath_hal *, AR5K_CHIP);
extern void ath5k_hw_detach(struct ath_hal *);
/* Reset */
@@ -1344,7 +1343,6 @@
extern AR5K_STATUS ath5k_hw_proc_new_rx_status(struct ath_hal *, struct
ath5k_desc *,
u_int32_t phyAddr, struct
ath5k_desc *next);
-
/* GPIO */
extern void ath5k_hw_set_ledstate(struct ath_hal*, AR5K_LED_STATE);
extern AR5K_BOOL ath5k_hw_set_gpio_output(struct ath_hal *, u_int32_t
gpio);
@@ -1356,38 +1354,31 @@
ieee80211_regdomain_t ath5k_regdomain_to_ieee(u_int16_t);
extern u_int16_t ath5k_hw_get_regdomain(struct ath_hal*);
+
+/*
+ * Prototypes - PHY functions
+ */
+
/* Channel/RF setup */
-AR5K_BOOL ath5k_hw_check_channel(struct ath_hal *, u_int16_t,
u_int flags);
+extern AR5K_BOOL ath5k_hw_check_channel(struct ath_hal *, u_int16_t,
u_int flags);
extern AR5K_BOOL ath5k_hw_phy_calibrate(struct ath_hal*, AR5K_CHANNEL *);
-AR5K_BOOL ath5k_hw_channel(struct ath_hal *, AR5K_CHANNEL *);
-u_int32_t ath5k_hw_rf5110_chan2athchan(AR5K_CHANNEL *);
-AR5K_BOOL ath5k_hw_rf5110_channel(struct ath_hal *, AR5K_CHANNEL
*);
-AR5K_BOOL ath5k_hw_rf5111_chan2athchan(u_int, struct
ath5k_athchan_2ghz *);
-AR5K_BOOL ath5k_hw_rf5111_channel(struct ath_hal *, AR5K_CHANNEL
*);
-AR5K_BOOL ath5k_hw_rf5112_channel(struct ath_hal *, AR5K_CHANNEL
*);
-AR5K_BOOL ath5k_hw_phy_calibrate(struct ath_hal *hal,
AR5K_CHANNEL *channel);
-AR5K_BOOL ath5k_hw_rf5110_calibrate(struct ath_hal *hal,
AR5K_CHANNEL *channel);
-AR5K_BOOL ath5k_hw_rf511x_calibrate(struct ath_hal *hal,
AR5K_CHANNEL *channel);
+extern AR5K_BOOL ath5k_hw_channel(struct ath_hal *, AR5K_CHANNEL *);
+extern AR5K_BOOL ath5k_hw_phy_calibrate(struct ath_hal *hal,
AR5K_CHANNEL *channel);
extern AR5K_BOOL ath5k_hw_phy_disable(struct ath_hal *);
extern void ath5k_hw_set_def_antenna(struct ath_hal *, u_int);
extern u_int ath5k_hw_get_def_antenna(struct ath_hal *);
-u_int ath5k_hw_rfregs_op(u_int32_t *, u_int32_t, u_int32_t,
u_int32_t,
- u_int32_t, u_int32_t,
AR5K_BOOL);
-u_int32_t ath5k_hw_rfregs_gainf_corr(struct ath_hal *);
-AR5K_BOOL ath5k_hw_rfregs_gain_readback(struct ath_hal *);
-int32_t ath5k_hw_rfregs_gain_adjust(struct ath_hal *);
-AR5K_BOOL ath5k_hw_rfregs(struct ath_hal *, AR5K_CHANNEL *,
u_int);
-AR5K_BOOL ath5k_hw_rf5111_rfregs(struct ath_hal *, AR5K_CHANNEL
*, u_int);
-AR5K_BOOL ath5k_hw_rf5112_rfregs(struct ath_hal *, AR5K_CHANNEL
*, u_int);
-void ath5k_hw_ar5211_rfregs(struct ath_hal *, AR5K_CHANNEL
*, u_int, u_int);
-AR5K_BOOL ath5k_hw_rfgain(struct ath_hal *, u_int);
+extern AR5K_BOOL ath5k_hw_rfgain(struct ath_hal *, u_int);
extern AR5K_RFGAIN ath5k_hw_get_rf_gain(struct ath_hal*);
-void ath5k_hw_txpower_table(struct ath_hal *, AR5K_CHANNEL
*, int16_t);
-AR5K_BOOL ath5k_hw_txpower(struct ath_hal *, AR5K_CHANNEL *,
u_int);
+extern AR5K_BOOL ath5k_hw_txpower(struct ath_hal *, AR5K_CHANNEL *,
u_int);
extern AR5K_BOOL ath5k_hw_set_txpower_limit(struct ath_hal *, u_int);
+extern void ath5k_hw_set_rfgain_opt(struct ath_hal *hal);
+extern AR5K_BOOL ath5k_hw_rfregs(struct ath_hal *hal, AR5K_CHANNEL
*channel, u_int mode);
+extern u_int16_t ath5k_hw_radio_revision(struct ath_hal *hal, AR5K_CHIP
chip);
-
-/* Misc */
+/* Misc TODO: Clean them up ! */
+extern void ath5k_write_initvals(struct ath_hal *hal, u_int8_t
mode, AR5K_BOOL change_channel);
+extern AR5K_BOOL ath5k_hw_register_timeout(struct ath_hal *hal,
u_int32_t reg, u_int32_t flag,
+ u_int32_t val, AR5K_BOOL
is_set);
extern void ath5k_hw_dump_state(struct ath_hal *);
extern AR5K_BOOL ath5k_hw_has_veol(struct ath_hal *);
extern void ath5k_hw_get_tx_inter_queue(struct ath_hal *, u_int32_t
*);
@@ -1453,8 +1444,41 @@
void ath5k_reset_tsf(struct ieee80211_hw *hw);
-/*ah_osdep.c*/
-struct ath_hal * _ath_hal_attach(u_int16_t devid, AR5K_SOFTC sc, AR5K_BUS_TAG
t,
- AR5K_BUS_HANDLE h, void* s);
-void ath_hal_detach(struct ath_hal *hal);
+/*
+ * Read from a device register
+ */
+static inline u32 ath5k_hw_reg_read(struct ath_hal *hal, u16 reg)
+{
+ return readl(hal->ah_sh + reg);
+}
+
+/*
+ * Write to a device register
+ */
+static inline void ath5k_hw_reg_write(struct ath_hal *hal, u32 val, u16 reg)
+{
+ writel(val, hal->ah_sh + reg);
+}
+
+static inline __u16 ath5k_hw_unaligned_read_16(__le16 *p)
+{
+ return le16_to_cpu(get_unaligned(p));
+}
+
+static inline void ath5k_hw_unaligned_write_16(__u16 v, __le16* p)
+{
+ put_unaligned(cpu_to_le16(v), p);
+}
+
+static inline __u32 ath5k_hw_unaligned_read_32(__le32 *p)
+{
+ return le32_to_cpu(get_unaligned(p));
+}
+
+static inline void ath5k_hw_unaligned_write_32(__u32 v, __le32 *p)
+{
+ put_unaligned(cpu_to_le32(v), p);
+}
+
+
#endif /* _AR5K_H */
Modified: branches/ath5k/ath5k_hw.c
===================================================================
--- branches/ath5k/ath5k_hw.c 2007-08-26 09:34:43 UTC (rev 2670)
+++ branches/ath5k/ath5k_hw.c 2007-08-26 16:17:52 UTC (rev 2671)
@@ -96,39 +96,8 @@
* Initial register dumps
*/
-/*
- * MAC/PHY Settings
- */
-/* Common for all modes */
-static const struct ath5k_ini ar5210_ini[] = AR5K_AR5210_INI;
-static const struct ath5k_ini ar5211_ini[] = AR5K_AR5211_INI;
-static const struct ath5k_ini ar5212_ini[] = AR5K_AR5212_INI;
-/* Mode-specific settings */
-static const struct ath5k_ini_mode ar5211_ini_mode[] = AR5K_AR5211_INI_MODE;
-static const struct ath5k_ini_mode ar5212_ini_mode[] = AR5K_AR5212_INI_MODE;
-static const struct ath5k_ini_mode ar5212_rf5111_ini_mode[] =
AR5K_AR5212_RF5111_INI_MODE;
-static const struct ath5k_ini_mode ar5212_rf5112_ini_mode[] =
AR5K_AR5212_RF5112_INI_MODE;
-/* RF Initial BB gain settings */
-static const struct ath5k_ini rf5111_ini_bbgain[] = AR5K_RF5111_INI_BBGAIN;
-static const struct ath5k_ini rf5112_ini_bbgain[] = AR5K_RF5112_INI_BBGAIN;
-
/*
- * RF Settings
- */
-/* RF Banks */
-static const struct ath5k_ini_rf rf5111_rf[] = AR5K_RF5111_INI_RF;
-static const struct ath5k_ini_rf rf5112_rf[] = AR5K_RF5112_INI_RF;
-static const struct ath5k_ini_rf rf5112a_rf[] = AR5K_RF5112A_INI_RF;
-/* Initial mode-specific RF gain table for 5111/5112 */
-static const struct ath5k_ini_rfgain rf5111_ini_rfgain[] =
AR5K_RF5111_INI_RFGAIN;
-static const struct ath5k_ini_rfgain rf5112_ini_rfgain[] =
AR5K_RF5112_INI_RFGAIN;
-/* Initial gain optimization tables */
-static const struct ath5k_gain_opt rf5111_gain_opt = AR5K_RF5111_GAIN_OPT;
-static const struct ath5k_gain_opt rf5112_gain_opt = AR5K_RF5112_GAIN_OPT;
-
-
-/*
* Enable to overwrite the country code (use "00" for debug)
*/
#if 0
@@ -241,19 +210,6 @@
* Functions used internaly
*/
-static u_int32_t
-ath5k_hw_bitswap(u_int32_t val, u_int bits)
-{
- u_int32_t retval = 0, bit, i;
-
- for (i = 0; i < bits; i++) {
- bit = (val >> i) & 1;
- retval = (retval << 1) | bit;
- }
-
- return (retval);
-}
-
inline u_int
ath5k_hw_htoclock(u_int usec, AR5K_BOOL turbo)
{
@@ -306,45 +262,9 @@
}
/*
- * Read from a device register
- */
-static inline u32 ath5k_hw_reg_read(struct ath_hal *hal, u16 reg)
-{
- return readl(hal->ah_sh + reg);
-}
-
-/*
- * Write to a device register
- */
-static inline void ath5k_hw_reg_write(struct ath_hal *hal, u32 val, u16 reg)
-{
- writel(val, hal->ah_sh + reg);
-}
-
-static inline __u16 ath5k_hw_unaligned_read_16(__le16 *p)
-{
- return le16_to_cpu(get_unaligned(p));
-}
-
-static inline void ath5k_hw_unaligned_write_16(__u16 v, __le16* p)
-{
- put_unaligned(cpu_to_le16(v), p);
-}
-
-static inline __u32 ath5k_hw_unaligned_read_32(__le32 *p)
-{
- return le32_to_cpu(get_unaligned(p));
-}
-
-static inline void ath5k_hw_unaligned_write_32(__u32 v, __le32 *p)
-{
- put_unaligned(cpu_to_le32(v), p);
-}
-
-/*
* Check if a register write has been completed
*/
-static AR5K_BOOL
+AR5K_BOOL
ath5k_hw_register_timeout(struct ath_hal *hal, u_int32_t reg, u_int32_t flag,
u_int32_t val, AR5K_BOOL is_set)
{
@@ -366,52 +286,6 @@
return (TRUE);
}
-/*
- * Write initial register dump
- */
-static void
-ath5k_hw_ini_registers(struct ath_hal *hal, int size,
- const struct ath5k_ini *ini_regs, AR5K_BOOL change_channel)
-{
- int i;
-
- /* Write initial registers */
- for (i = 0; i < size ; i++) {
- /* On channel change there is
- * no need to mess with PCU */
- if (change_channel == TRUE &&
- ini_regs[i].ini_register >= AR5K_PCU_MIN &&
- ini_regs[i].ini_register <= AR5K_PCU_MAX)
- continue;
-
- switch (ini_regs[i].ini_mode) {
- case AR5K_INI_READ:
- /* Cleared on read */
- AR5K_REG_READ(ini_regs[i].ini_register);
- break;
- case AR5K_INI_WRITE:
- default:
- AR5K_REG_WAIT(i);
- AR5K_REG_WRITE(ini_regs[i].ini_register,
- ini_regs[i].ini_value);
- }
- }
-}
-
-static void
-ath5k_hw_ini_mode_registers(struct ath_hal *hal, int size,
- const struct ath5k_ini_mode *ini_mode, u_int8_t mode)
-{
- int i;
-
- for (i = 0; i < size; i++) {
- AR5K_REG_WAIT(i);
- AR5K_REG_WRITE((u_int32_t)ini_mode[i].mode_register,
- ini_mode[i].mode_value[mode]);
- }
-
-}
-
/***************************************\
Attach/Detach Functions
\***************************************/
@@ -582,33 +456,15 @@
ath5k_hw_set_lladdr(hal, mac);
- /* Initialize the gain optimization values */
- /*For RF5111*/
- if (hal->ah_radio == AR5K_RF5111) {
- hal->ah_gain.g_step_idx = rf5111_gain_opt.go_default;
- hal->ah_gain.g_step =
- &rf5111_gain_opt.go_step[hal->ah_gain.g_step_idx];
- hal->ah_gain.g_low = 20;
- hal->ah_gain.g_high = 35;
- hal->ah_gain.g_active = 1;
- /*For RF5112*/
- } else if (hal->ah_radio == AR5K_RF5112) {
- hal->ah_gain.g_step_idx = rf5112_gain_opt.go_default;
- hal->ah_gain.g_step =
- &rf5111_gain_opt.go_step[hal->ah_gain.g_step_idx];
- hal->ah_gain.g_low = 20;
- hal->ah_gain.g_high = 85;
- hal->ah_gain.g_active = 1;
- }
-
+ ath5k_hw_set_rfgain_opt(hal);
*status = AR5K_OK;
- printk(KERN_INFO "ath_hal: Atheros HW found \n");
- printk(KERN_INFO "ath_hal: MAC version: %s\n",
+ printk(KERN_INFO "ath5k: Atheros HW found \n");
+ printk(KERN_INFO "ath5k: MAC version: %s\n",
ath5k_hw_get_part_name(AR5K_VERSION_VER,hal->ah_mac_srev));
- printk(KERN_INFO "ath_hal: PHY version: %s\n",
+ printk(KERN_INFO "ath5k: PHY version: %s\n",
ath5k_hw_get_part_name(AR5K_VERSION_RAD,hal->ah_radio_5ghz_revision));
- printk(KERN_INFO "ath_hal: EEPROM version: %x.%x\n",
+ printk(KERN_INFO "ath5k: EEPROM version: %x.%x\n",
(hal->ah_ee_version & 0xF000) >> 12, hal->ah_ee_version &
0xFFF);
return (hal);
@@ -765,56 +621,6 @@
}
/*
- * Get the PHY Chip revision
- */
-u_int16_t
-ath5k_hw_radio_revision(struct ath_hal *hal, AR5K_CHIP chip)
-{
- int i;
- u_int32_t srev;
- u_int16_t ret;
-
- AR5K_TRACE;
-
- /*
- * Set the radio chip access register
- */
- switch (chip) {
- case AR5K_CHIP_2GHZ:
- AR5K_REG_WRITE(AR5K_PHY(0), AR5K_PHY_SHIFT_2GHZ);
- break;
- case AR5K_CHIP_5GHZ:
- AR5K_REG_WRITE(AR5K_PHY(0), AR5K_PHY_SHIFT_5GHZ);
- break;
- default:
- return (0);
- }
-
- udelay(2000);
-
- /* ...wait until PHY is ready and read the selected radio revision */
- AR5K_REG_WRITE(AR5K_PHY(0x34), 0x00001c16);
-
- for (i = 0; i < 8; i++)
- AR5K_REG_WRITE(AR5K_PHY(0x20), 0x00010000);
-
- if (hal->ah_version == AR5K_AR5210) {
- srev = AR5K_REG_READ(AR5K_PHY(256) >> 28) & 0xf;
-
- ret = (u_int16_t) ath5k_hw_bitswap(srev, 4) + 1;
- } else {
- srev = (AR5K_REG_READ(AR5K_PHY(0x100)) >> 24) & 0xff;
-
- ret = (u_int16_t) ath5k_hw_bitswap(((srev & 0xf0) >> 4) |
((srev & 0x0f) << 4), 8);
- }
-
- /* Reset to the 5GHz mode */
- AR5K_REG_WRITE(AR5K_PHY(0), AR5K_PHY_SHIFT_5GHZ);
-
- return (ret);
-}
-
-/*
* Free the hal struct
*/
void
@@ -953,60 +759,9 @@
}
- /*
- * Write initial mode-specific settings
- */
- /*For 5212*/
- if (hal->ah_version == AR5K_AR5212) {
- ath5k_hw_ini_mode_registers(hal, AR5K_ELEMENTS(ar5212_ini_mode),
- ar5212_ini_mode, mode);
- if (hal->ah_radio == AR5K_RF5111) {
- ath5k_hw_ini_mode_registers(hal,
AR5K_ELEMENTS(ar5212_rf5111_ini_mode),
- ar5212_rf5111_ini_mode,
mode);
- } else if (hal->ah_radio == AR5K_RF5112) {
- ath5k_hw_ini_mode_registers(hal,
AR5K_ELEMENTS(ar5212_rf5112_ini_mode),
- ar5212_rf5112_ini_mode,
mode);
- }
- }
- /*For 5211*/
- if (hal->ah_version == AR5K_AR5211) {
- ath5k_hw_ini_mode_registers(hal, AR5K_ELEMENTS(ar5211_ini_mode),
- ar5211_ini_mode, mode);
- }
- /* For 5210 mode settings check out ath5k_hw_reset_tx_queue */
+ ath5k_write_initvals(hal, mode, change_channel);
/*
- * Write initial settings common for all modes
- */
- if (hal->ah_version == AR5K_AR5212) {
- ath5k_hw_ini_registers(hal, AR5K_ELEMENTS(ar5212_ini),
- ar5212_ini, change_channel);
- if (hal->ah_radio == AR5K_RF5112) {
- AR5K_REG_WRITE(AR5K_PHY_PAPD_PROBE,
- AR5K_PHY_PAPD_PROBE_INI_5112);
- ath5k_hw_ini_registers(hal,
AR5K_ELEMENTS(rf5112_ini_bbgain),
- rf5112_ini_bbgain,
change_channel);
- } else if (hal->ah_radio == AR5K_RF5111) {
- AR5K_REG_WRITE( AR5K_PHY_GAIN_2GHZ,
- AR5K_PHY_GAIN_2GHZ_INI_5111);
- AR5K_REG_WRITE( AR5K_PHY_PAPD_PROBE,
- AR5K_PHY_PAPD_PROBE_INI_5111 );
- ath5k_hw_ini_registers(hal,
AR5K_ELEMENTS(rf5111_ini_bbgain),
- rf5111_ini_bbgain,
change_channel);
- }
- } else if (hal->ah_version == AR5K_AR5211) {
- ath5k_hw_ini_registers(hal, AR5K_ELEMENTS(ar5211_ini),
- ar5211_ini, change_channel);
- /* AR5211 only comes with 5111 */
- ath5k_hw_ini_registers(hal, AR5K_ELEMENTS(rf5111_ini_bbgain),
- rf5111_ini_bbgain, change_channel);
- } else if (hal->ah_version == AR5K_AR5210) {
- ath5k_hw_ini_registers(hal, AR5K_ELEMENTS(ar5210_ini),
- ar5210_ini, change_channel);
- }
-
-
- /*
* 5211/5212 Specific
*/
if (hal->ah_version != AR5K_AR5210) {
@@ -4750,36 +4505,12 @@
\*********************************/
/*
- * Following 2 functions come from net80211
* TODO: These do not belong here, they have nothing
* to do with hw. I left them here temporarily for
* combatibility.
* M.F.
*/
-/*
- * Check if a channel is inside supported range
- */
-AR5K_BOOL
-ath5k_hw_check_channel(struct ath_hal *hal, u_int16_t freq, u_int flags)
-{
- /* Check if the channel is in our supported range */
- if (flags & CHANNEL_2GHZ) {
- if ((freq >= hal->ah_capabilities.cap_range.range_2ghz_min) &&
- (freq <= hal->ah_capabilities.cap_range.range_2ghz_max))
- return (TRUE);
- } else if (flags & CHANNEL_5GHZ)
- if ((freq >= hal->ah_capabilities.cap_range.range_5ghz_min) &&
- (freq <= hal->ah_capabilities.cap_range.range_5ghz_max))
- return (TRUE);
-
- return (FALSE);
-}
-
-/*
- * Regdomain stuff, these also don't belong here etc
- */
-
u_int16_t
ath5k_regdomain_from_ieee(ieee80211_regdomain_t ieee)
{
@@ -4832,1077 +4563,6 @@
return (regdomain);
}
-
-
-
-/*************************\
- PHY/RF access functions
-\*************************/
-
-/*
- * Set a channel on the radio chip
- */
-AR5K_BOOL
-ath5k_hw_channel(struct ath_hal *hal, AR5K_CHANNEL *channel)
-{
- AR5K_BOOL ret;
-
- /*
- * Check bounds supported by the PHY
- * (don't care about regulation restrictions at this point)
- */
- if ((channel->freq < hal->ah_capabilities.cap_range.range_2ghz_min ||
- channel->freq > hal->ah_capabilities.cap_range.range_2ghz_max) &&
- (channel->freq < hal->ah_capabilities.cap_range.range_5ghz_min ||
- channel->freq > hal->ah_capabilities.cap_range.range_5ghz_max)) {
- AR5K_PRINTF("channel out of supported range (%u MHz)\n",
- channel->freq);
- return (FALSE);
- }
-
- /*
- * Set the channel and wait
- */
- if (hal->ah_radio == AR5K_RF5110)
- ret = ath5k_hw_rf5110_channel(hal, channel);
- else if (hal->ah_radio == AR5K_RF5111)
- ret = ath5k_hw_rf5111_channel(hal, channel);
- else
- ret = ath5k_hw_rf5112_channel(hal, channel);
-
- if (ret == FALSE)
- return (ret);
-
- hal->ah_current_channel.freq = channel->freq;
- hal->ah_current_channel.channel_flags = channel->channel_flags;
- hal->ah_turbo = channel->channel_flags == CHANNEL_T ?
- TRUE : FALSE;
-
- return (TRUE);
-}
-
-/*
- * Convertion needed for RF5110
- */
-u_int32_t
-ath5k_hw_rf5110_chan2athchan(AR5K_CHANNEL *channel)
-{
- u_int32_t athchan;
-
- /*
- * Convert IEEE channel/MHz to an internal channel value used
- * by the AR5210 chipset. This has not been verified with
- * newer chipsets like the AR5212A who have a completely
- * different RF/PHY part.
- */
- athchan = (ath5k_hw_bitswap((ath5k_mhz2ieee(channel->freq,
- channel->channel_flags) - 24) / 2, 5) << 1) |
- (1 << 6) | 0x1;
-
- return (athchan);
-}
-
-/*
- * Set channel on RF5110
- */
-AR5K_BOOL
-ath5k_hw_rf5110_channel(struct ath_hal *hal, AR5K_CHANNEL *channel)
-{
- u_int32_t data;
-
- /*
- * Set the channel and wait
- */
- data = ath5k_hw_rf5110_chan2athchan(channel);
- AR5K_REG_WRITE(AR5K_RF_BUFFER, data);
- AR5K_REG_WRITE(AR5K_RF_BUFFER_CONTROL_0, 0);
- udelay(1000);
-
- return (TRUE);
-}
-
-/*
- * Convertion needed for 5111
- */
-AR5K_BOOL
-ath5k_hw_rf5111_chan2athchan(u_int ieee, struct ath5k_athchan_2ghz *athchan)
-{
- int channel;
-
- /* Cast this value to catch negative channel numbers (>= -19) */
- channel = (int)ieee;
-
- /*
- * Map 2GHz IEEE channel to 5GHz Atheros channel
- */
- if (channel <= 13) {
- athchan->a2_athchan = 115 + channel;
- athchan->a2_flags = 0x46;
- } else if (channel == 14) {
- athchan->a2_athchan = 124;
- athchan->a2_flags = 0x44;
- } else if (channel >= 15 && channel <= 26) {
- athchan->a2_athchan = ((channel - 14) * 4) + 132;
- athchan->a2_flags = 0x46;
- } else
- return (FALSE);
-
- return (TRUE);
-}
-
-/*
- * Set channel on 5111
- */
-AR5K_BOOL
-ath5k_hw_rf5111_channel(struct ath_hal *hal, AR5K_CHANNEL *channel)
-{
- u_int ieee_channel, ath_channel;
- u_int32_t data0, data1, clock;
- struct ath5k_athchan_2ghz ath_channel_2ghz;
-
- /*
- * Set the channel on the RF5111 radio
- */
- data0 = data1 = 0;
- ath_channel = ieee_channel = ath5k_mhz2ieee(channel->freq,
- channel->channel_flags);
-
- if (channel->channel_flags & CHANNEL_2GHZ) {
- /* Map 2GHz channel to 5GHz Atheros channel ID */
- if (ath5k_hw_rf5111_chan2athchan(ieee_channel,
- &ath_channel_2ghz) == FALSE)
- return (FALSE);
-
- ath_channel = ath_channel_2ghz.a2_athchan;
- data0 = ((ath5k_hw_bitswap(ath_channel_2ghz.a2_flags, 8) & 0xff)
- << 5) | (1 << 4);
- }
-
- if (ath_channel < 145 || !(ath_channel & 1)) {
- clock = 1;
- data1 = ((ath5k_hw_bitswap(ath_channel - 24, 8) & 0xff) << 2)
- | (clock << 1) | (1 << 10) | 1;
- } else {
- clock = 0;
- data1 = ((ath5k_hw_bitswap((ath_channel - 24) / 2, 8) & 0xff)
<< 2)
- | (clock << 1) | (1 << 10) | 1;
- }
-
- AR5K_REG_WRITE(AR5K_RF_BUFFER, (data1 & 0xff) | ((data0 & 0xff) << 8));
- AR5K_REG_WRITE(AR5K_RF_BUFFER_CONTROL_3, ((data1 >> 8) & 0xff) | (data0
& 0xff00));
-
- return (TRUE);
-}
-
-/*
- * Set channel on 5112
- */
-AR5K_BOOL
-ath5k_hw_rf5112_channel(struct ath_hal *hal, AR5K_CHANNEL *channel)
-{
- u_int32_t data, data0, data1, data2;
- u_int16_t c;
-
- data = data0 = data1 = data2 = 0;
- c = channel->freq;
-
- /*
- * Set the channel on the RF5112 or newer
- */
- if (c < 4800) {
- if (!((c - 2224) % 5)) {
- data0 = ((2 * (c - 704)) - 3040) / 10;
- data1 = 1;
- } else if (!((c - 2192) % 5)) {
- data0 = ((2 * (c - 672)) - 3040) / 10;
- data1 = 0;
- } else
- return (FALSE);
-
- data0 = ath5k_hw_bitswap((data0 << 2) & 0xff, 8);
- } else {
- if (!(c % 20) && c >= 5120) {
- data0 = ath5k_hw_bitswap(((c - 4800) / 20 << 2), 8);
- data2 = ath5k_hw_bitswap(3, 2);
- } else if (!(c % 10)) {
- data0 = ath5k_hw_bitswap(((c - 4800) / 10 << 1), 8);
- data2 = ath5k_hw_bitswap(2, 2);
- } else if (!(c % 5)) {
- data0 = ath5k_hw_bitswap((c - 4800) / 5, 8);
- data2 = ath5k_hw_bitswap(1, 2);
- } else
- return (FALSE);
- }
-
- data = (data0 << 4) | (data1 << 1) | (data2 << 2) | 0x1001;
-
- AR5K_REG_WRITE(AR5K_RF_BUFFER, data & 0xff);
- AR5K_REG_WRITE(AR5K_RF_BUFFER_CONTROL_5, (data >> 8) & 0x7f);
-
- return (TRUE);
-}
-
-/*
- * Perform a PHY calibration
- */
-AR5K_BOOL
-ath5k_hw_phy_calibrate(struct ath_hal *hal, AR5K_CHANNEL *channel){
-
- AR5K_BOOL ret;
-
- if (hal->ah_radio == AR5K_RF5110)
- ret = ath5k_hw_rf5110_calibrate(hal,channel);
- else
- ret = ath5k_hw_rf511x_calibrate(hal,channel);
-
- return (ret);
-}
-/*
- * Perform a PHY calibration on RF5110
- */
-AR5K_BOOL
-ath5k_hw_rf5110_calibrate(struct ath_hal *hal, AR5K_CHANNEL *channel)
-{
- AR5K_BOOL ret = TRUE;
- u_int32_t phy_sig, phy_agc, phy_sat, beacon, noise_floor;
- u_int i;
-
-#define AGC_DISABLE { \
- AR5K_REG_ENABLE_BITS(AR5K_PHY_AGC, \
- AR5K_PHY_AGC_DISABLE); \
- udelay(10); \
-}
-
-#define AGC_ENABLE { \
- AR5K_REG_DISABLE_BITS(AR5K_PHY_AGC, \
- AR5K_PHY_AGC_DISABLE); \
-}
-
- /*
- * Disable beacons and RX/TX queues, wait
- */
- AR5K_REG_ENABLE_BITS(AR5K_DIAG_SW_5210,
- AR5K_DIAG_SW_DIS_TX | AR5K_DIAG_SW_DIS_RX_5210);
- beacon = AR5K_REG_READ(AR5K_BEACON_5210);
- AR5K_REG_WRITE(AR5K_BEACON_5210, beacon & ~AR5K_BEACON_ENABLE);
-
- udelay(2300);
-
- /*
- * Set the channel (with AGC turned off)
- */
- AGC_DISABLE;
- ret = ath5k_hw_channel(hal, channel);
-
- /*
- * Activate PHY and wait
- */
- AR5K_REG_WRITE(AR5K_PHY_ACT, AR5K_PHY_ACT_ENABLE);
- udelay(1000);
-
- AGC_ENABLE;
-
- if (ret == FALSE)
- return (ret);
-
- /*
- * Calibrate the radio chip
- */
-
- /* Remember normal state */
- phy_sig = AR5K_REG_READ(AR5K_PHY_SIG);
- phy_agc = AR5K_REG_READ(AR5K_PHY_AGCCOARSE);
- phy_sat = AR5K_REG_READ(AR5K_PHY_ADCSAT);
-
- /* Update radio registers */
- AR5K_REG_WRITE(AR5K_PHY_SIG,
- (phy_sig & ~(AR5K_PHY_SIG_FIRPWR)) |
- AR5K_REG_SM(-1, AR5K_PHY_SIG_FIRPWR));
-
- AR5K_REG_WRITE(AR5K_PHY_AGCCOARSE,
- (phy_agc & ~(AR5K_PHY_AGCCOARSE_HI |
- AR5K_PHY_AGCCOARSE_LO)) |
- AR5K_REG_SM(-1, AR5K_PHY_AGCCOARSE_HI) |
- AR5K_REG_SM(-127, AR5K_PHY_AGCCOARSE_LO));
-
- AR5K_REG_WRITE(AR5K_PHY_ADCSAT,
- (phy_sat & ~(AR5K_PHY_ADCSAT_ICNT |
- AR5K_PHY_ADCSAT_THR)) |
- AR5K_REG_SM(2, AR5K_PHY_ADCSAT_ICNT) |
- AR5K_REG_SM(12, AR5K_PHY_ADCSAT_THR));
-
- udelay(20);
-
- AGC_DISABLE;
- AR5K_REG_WRITE(AR5K_PHY_RFSTG, AR5K_PHY_RFSTG_DISABLE);
- AGC_ENABLE;
-
- udelay(1000);
-
- /*
- * Enable calibration and wait until completion
- */
- AR5K_REG_ENABLE_BITS(AR5K_PHY_AGCCTL,
- AR5K_PHY_AGCCTL_CAL);
-
- if (ath5k_hw_register_timeout(hal, AR5K_PHY_AGCCTL,
- AR5K_PHY_AGCCTL_CAL, 0, FALSE) == FALSE) {
- AR5K_PRINTF("calibration timeout (%uMHz)\n",
- channel->freq);
- ret = FALSE;
- }
-
- /* Reset to normal state */
- AR5K_REG_WRITE(AR5K_PHY_SIG, phy_sig);
- AR5K_REG_WRITE(AR5K_PHY_AGCCOARSE, phy_agc);
- AR5K_REG_WRITE(AR5K_PHY_ADCSAT, phy_sat);
-
- if (ret == FALSE)
- return (FALSE);
-
- /*
- * Enable noise floor calibration and wait until completion
- */
- AR5K_REG_ENABLE_BITS(AR5K_PHY_AGCCTL,
- AR5K_PHY_AGCCTL_NF);
-
- if (ath5k_hw_register_timeout(hal, AR5K_PHY_AGCCTL,
- AR5K_PHY_AGCCTL_NF, 0, FALSE) == FALSE) {
- AR5K_PRINTF("noise floor calibration timeout (%uMHz)\n",
- channel->freq);
- return (FALSE);
- }
-
- /* Wait until the noise floor is calibrated */
- for (i = 20; i > 0; i--) {
- udelay(1000);
- noise_floor = AR5K_REG_READ(AR5K_PHY_NF);
-
- if (AR5K_PHY_NF_RVAL(noise_floor) &
- AR5K_PHY_NF_ACTIVE)
- noise_floor = AR5K_PHY_NF_AVAL(noise_floor);
-
- if (noise_floor <= AR5K_TUNE_NOISE_FLOOR)
- break;
- }
-
- if (noise_floor > AR5K_TUNE_NOISE_FLOOR) {
- AR5K_PRINTF("noise floor calibration failed (%uMHz)\n",
- channel->freq);
- return (FALSE);
- }
-
-
- /*
- * Re-enable RX/TX and beacons
- */
- AR5K_REG_DISABLE_BITS(AR5K_DIAG_SW_5210,
- AR5K_DIAG_SW_DIS_TX | AR5K_DIAG_SW_DIS_RX_5210);
- AR5K_REG_WRITE(AR5K_BEACON_5210, beacon);
-
-#undef AGC_ENABLE
-#undef AGC_DISABLE
-
- return (TRUE);
-}
-
-/*
- * Perform a PHY calibration on RF5111/5112
- * (Sync I/Q for inter-symbol interference)
- */
-AR5K_BOOL
-ath5k_hw_rf511x_calibrate(struct ath_hal *hal, AR5K_CHANNEL *channel)
-{
- u_int32_t i_pwr, q_pwr;
- int32_t iq_corr, i_coff, i_coffd, q_coff, q_coffd;
- AR5K_TRACE;
-
- if (hal->ah_calibration == FALSE ||
- AR5K_REG_READ(AR5K_PHY_IQ) & AR5K_PHY_IQ_RUN)
- goto done;
-
- hal->ah_calibration = FALSE;
-
- iq_corr = AR5K_REG_READ(AR5K_PHY_IQRES_CAL_CORR);
- i_pwr = AR5K_REG_READ(AR5K_PHY_IQRES_CAL_PWR_I);
- q_pwr = AR5K_REG_READ(AR5K_PHY_IQRES_CAL_PWR_Q);
- i_coffd = ((i_pwr >> 1) + (q_pwr >> 1)) >> 7;
- q_coffd = q_pwr >> 6;
-
- if (i_coffd == 0 || q_coffd == 0)
- goto done;
-
- i_coff = ((-iq_corr) / i_coffd) & 0x3f;
- q_coff = (((int32_t)i_pwr / q_coffd) - 64) & 0x1f;
-
- /* Commit new IQ value */
- AR5K_REG_ENABLE_BITS(AR5K_PHY_IQ,
- AR5K_PHY_IQ_CORR_ENABLE |
- ((u_int32_t)q_coff) |
- ((u_int32_t)i_coff << AR5K_PHY_IQ_CORR_Q_I_COFF_S));
-
- done:
- /* Start noise floor calibration */
- AR5K_REG_ENABLE_BITS(AR5K_PHY_AGCCTL,
- AR5K_PHY_AGCCTL_NF);
-
- /* Request RF gain */
- if (channel->channel_flags & CHANNEL_5GHZ) {
- AR5K_REG_WRITE(AR5K_PHY_PAPD_PROBE,
- AR5K_REG_SM(hal->ah_txpower.txp_max,
- AR5K_PHY_PAPD_PROBE_TXPOWER) |
- AR5K_PHY_PAPD_PROBE_TX_NEXT);
- hal->ah_rf_gain = AR5K_RFGAIN_READ_REQUESTED;
- }
-
- return (TRUE);
-}
-
-AR5K_BOOL
-ath5k_hw_phy_disable(struct ath_hal *hal)
-{
- AR5K_TRACE;
- /*Just a try M.F.*/
- AR5K_REG_WRITE(AR5K_PHY_ACT, AR5K_PHY_ACT_DISABLE);
- return (TRUE);
-}
-
-void /*TODO:Boundary check*/
-ath5k_hw_set_def_antenna(struct ath_hal *hal, u_int ant)
-{
- AR5K_TRACE;
- /*Just a try M.F.*/
- if (hal->ah_version != AR5K_AR5210)
- AR5K_REG_WRITE(AR5K_DEFAULT_ANTENNA, ant);
-
- return;
-}
-
-u_int
-ath5k_hw_get_def_antenna(struct ath_hal *hal)
-{
- AR5K_TRACE;
- /*Just a try M.F.*/
- if (hal->ah_version != AR5K_AR5210)
- return AR5K_REG_READ(AR5K_DEFAULT_ANTENNA);
-
- return (FALSE); /*XXX: What do we return for 5210 ?*/
-}
-
-/*
- * Used to modify RF Banks before writing them to AR5K_RF_BUFFER
- */
-u_int
-ath5k_hw_rfregs_op(u_int32_t *rf, u_int32_t offset, u_int32_t reg, u_int32_t
bits,
- u_int32_t first, u_int32_t col, AR5K_BOOL set)
-{
- u_int32_t mask, entry, last, data, shift, position;
- int32_t left;
- int i;
-
- data = 0;
-
- if (rf == NULL)
- /* should not happen */
- return (0);
-
- if (!(col <= 3 && bits <= 32 && first + bits <= 319)) {
- AR5K_PRINTF("invalid values at offset %u\n", offset);
- return (0);
- }
-
- entry = ((first - 1) / 8) + offset;
- position = (first - 1) % 8;
-
- if (set == TRUE)
- data = ath5k_hw_bitswap(reg, bits);
-
- for (i = shift = 0, left = bits; left > 0; position = 0, entry++, i++) {
- last = (position + left > 8) ? 8 : position + left;
- mask = (((1 << last) - 1) ^ ((1 << position) - 1)) <<
- (col * 8);
-
- if (set == TRUE) {
- rf[entry] &= ~mask;
- rf[entry] |= ((data << position) << (col * 8)) & mask;
- data >>= (8 - position);
- } else {
- data = (((rf[entry] & mask) >> (col * 8)) >>
- position) << shift;
- shift += last - position;
- }
-
- left -= 8 - position;
- }
-
- data = set == TRUE ? 1 : ath5k_hw_bitswap(data, bits);
-
- return (data);
-}
-
-u_int32_t
-ath5k_hw_rfregs_gainf_corr(struct ath_hal *hal)
-{
- u_int32_t mix, step;
- u_int32_t *rf;
-
- if (hal->ah_rf_banks == NULL)
- return (0);
-
- rf = hal->ah_rf_banks;
- hal->ah_gain.g_f_corr = 0;
-
- if (ath5k_hw_rfregs_op(rf, hal->ah_offset[7], 0, 1, 36, 0, FALSE) != 1)
- return (0);
-
- step = ath5k_hw_rfregs_op(rf, hal->ah_offset[7], 0, 4, 32, 0, FALSE);
- mix = hal->ah_gain.g_step->gos_param[0];
-
- switch (mix) {
- case 3:
- hal->ah_gain.g_f_corr = step * 2;
- break;
- case 2:
- hal->ah_gain.g_f_corr = (step - 5) * 2;
- break;
- case 1:
- hal->ah_gain.g_f_corr = step;
- break;
- default:
- hal->ah_gain.g_f_corr = 0;
- break;
- }
-
- return (hal->ah_gain.g_f_corr);
-}
-
-AR5K_BOOL
-ath5k_hw_rfregs_gain_readback(struct ath_hal *hal)
-{
- u_int32_t step, mix, level[4];
- u_int32_t *rf;
-
- if (hal->ah_rf_banks == NULL)
- return (0);
-
- rf = hal->ah_rf_banks;
-
- if (hal->ah_radio == AR5K_RF5111) {
- step = ath5k_hw_rfregs_op(rf, hal->ah_offset[7],
- 0, 6, 37, 0, FALSE);
- level[0] = 0;
- level[1] = (step == 0x3f) ? 0x32 : step + 4;
- level[2] = (step != 0x3f) ? 0x40 : level[0];
- level[3] = level[2] + 0x32;
-
- hal->ah_gain.g_high = level[3] -
- (step == 0x3f ? AR5K_GAIN_DYN_ADJUST_HI_MARGIN : -5);
- hal->ah_gain.g_low = level[0] +
- (step == 0x3f ? AR5K_GAIN_DYN_ADJUST_LO_MARGIN : 0);
- } else {
- mix = ath5k_hw_rfregs_op(rf, hal->ah_offset[7],
- 0, 1, 36, 0, FALSE);
- level[0] = level[2] = 0;
-
- if (mix == 1) {
- level[1] = level[3] = 83;
- } else {
- level[1] = level[3] = 107;
- hal->ah_gain.g_high = 55;
- }
- }
-
- return ((hal->ah_gain.g_current >= level[0] &&
- hal->ah_gain.g_current <= level[1]) ||
- (hal->ah_gain.g_current >= level[2] &&
- hal->ah_gain.g_current <= level[3]));
-}
-
-int32_t
-ath5k_hw_rfregs_gain_adjust(struct ath_hal *hal)
-{
- int ret = 0;
- const struct ath5k_gain_opt *go;
-
- go = hal->ah_radio == AR5K_RF5111 ?
- &rf5111_gain_opt : &rf5112_gain_opt;
-
- hal->ah_gain.g_step = &go->go_step[hal->ah_gain.g_step_idx];
-
- if (hal->ah_gain.g_current >= hal->ah_gain.g_high) {
- if (hal->ah_gain.g_step_idx == 0)
- return (-1);
- for (hal->ah_gain.g_target = hal->ah_gain.g_current;
- hal->ah_gain.g_target >= hal->ah_gain.g_high &&
- hal->ah_gain.g_step_idx > 0;
- hal->ah_gain.g_step =
- &go->go_step[hal->ah_gain.g_step_idx]) {
- hal->ah_gain.g_target -= 2 *
- (go->go_step[--(hal->ah_gain.g_step_idx)].gos_gain -
- hal->ah_gain.g_step->gos_gain);
- }
-
- ret = 1;
- goto done;
- }
-
- if (hal->ah_gain.g_current <= hal->ah_gain.g_low) {
- if (hal->ah_gain.g_step_idx == (go->go_steps_count - 1))
- return (-2);
- for (hal->ah_gain.g_target = hal->ah_gain.g_current;
- hal->ah_gain.g_target <= hal->ah_gain.g_low &&
- hal->ah_gain.g_step_idx < (go->go_steps_count - 1);
- hal->ah_gain.g_step =
- &go->go_step[hal->ah_gain.g_step_idx]) {
- hal->ah_gain.g_target -= 2 *
- (go->go_step[++(hal->ah_gain.g_step_idx)].gos_gain -
- hal->ah_gain.g_step->gos_gain);
- }
-
- ret = 2;
- goto done;
- }
-
- done:
-#ifdef AR5K_DEBUG
- AR5K_PRINTF("ret %d, gain step %u, current gain %u, target gain %u\n",
- ret,
- hal->ah_gain.g_step_idx,
- hal->ah_gain.g_current,
- hal->ah_gain.g_target);
-#endif
-
- return (ret);
-}
-
-/*
- * Initialize RF
- */
-AR5K_BOOL
-ath5k_hw_rfregs(struct ath_hal *hal, AR5K_CHANNEL *channel, u_int mode)
-{
- ath5k_rfgain_t *func = NULL;
- AR5K_BOOL ret;
-
- if (hal->ah_radio == AR5K_RF5111) {
- hal->ah_rf_banks_size = sizeof(rf5111_rf);
- func = ath5k_hw_rf5111_rfregs;
- } else if (hal->ah_radio == AR5K_RF5112) {
- if (hal->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A)
- hal->ah_rf_banks_size = sizeof(rf5112a_rf);
- else
- hal->ah_rf_banks_size = sizeof(rf5112_rf);
- func = ath5k_hw_rf5112_rfregs;
- } else
- return (FALSE);
-
- if (hal->ah_rf_banks == NULL) {
- /* XXX do extra checks? */
- if ((hal->ah_rf_banks = kmalloc(hal->ah_rf_banks_size,
- GFP_KERNEL)) == NULL) {
- AR5K_PRINT("out of memory\n");
- return (FALSE);
- }
- }
-
- ret = (func)(hal, channel, mode);
-
- if (ret == TRUE)
- hal->ah_rf_gain = AR5K_RFGAIN_INACTIVE;
-
- return (ret);
-}
-
-/*
- * Read EEPROM Calibration data, modify RF Banks and Initialize RF5111
- */
-AR5K_BOOL
-ath5k_hw_rf5111_rfregs(struct ath_hal *hal, AR5K_CHANNEL *channel, u_int mode)
-{
- struct ath5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom;
- const u_int rf_size = AR5K_ELEMENTS(rf5111_rf);
- u_int32_t *rf;
- int i, obdb = -1, bank = -1;
- u_int32_t ee_mode;
-
- AR5K_ASSERT_ENTRY(mode, AR5K_INI_VAL_MAX);
-
- rf = hal->ah_rf_banks;
-
- /* Copy values to modify them */
- for (i = 0; i < rf_size; i++) {
- if (rf5111_rf[i].rf_bank >=
- AR5K_RF5111_INI_RF_MAX_BANKS) {
- AR5K_PRINT("invalid bank\n");
- return (FALSE);
- }
-
- if (bank != rf5111_rf[i].rf_bank) {
- bank = rf5111_rf[i].rf_bank;
- hal->ah_offset[bank] = i;
- }
-
- rf[i] = rf5111_rf[i].rf_value[mode];
- }
-
- /* Modify bank 0 */
- if (channel->channel_flags & CHANNEL_2GHZ) {
- if (channel->channel_flags & CHANNEL_B)
- ee_mode = AR5K_EEPROM_MODE_11B;
- else
- ee_mode = AR5K_EEPROM_MODE_11G;
- obdb = 0;
-
- if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[0],
- ee->ee_ob[ee_mode][obdb], 3, 119, 0, TRUE))
- return (FALSE);
-
- if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[0],
- ee->ee_ob[ee_mode][obdb], 3, 122, 0, TRUE))
- return (FALSE);
-
- obdb = 1;
- /* Modify bank 6 */
- } else {
- /* For 11a, Turbo and XR */
- ee_mode = AR5K_EEPROM_MODE_11A;
- obdb = channel->freq >= 5725 ? 3 :
- (channel->freq >= 5500 ? 2 :
- (channel->freq >= 5260 ? 1 :
- (channel->freq > 4000 ? 0 : -1)));
-
- if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[6],
- ee->ee_pwd_84, 1, 51, 3, TRUE))
- return (FALSE);
-
- if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[6],
- ee->ee_pwd_90, 1, 45, 3, TRUE))
- return (FALSE);
- }
-
- if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[6],
- !ee->ee_xpd[ee_mode], 1, 95, 0, TRUE))
- return (FALSE);
-
- if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[6],
- ee->ee_x_gain[ee_mode], 4, 96, 0, TRUE))
- return (FALSE);
-
- if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[6],
- obdb >= 0 ? ee->ee_ob[ee_mode][obdb] : 0, 3, 104, 0, TRUE))
- return (FALSE);
-
- if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[6],
- obdb >= 0 ? ee->ee_db[ee_mode][obdb] : 0, 3, 107, 0, TRUE))
- return (FALSE);
-
- /* Modify bank 7 */
- if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[7],
- ee->ee_i_gain[ee_mode], 6, 29, 0, TRUE))
- return (FALSE);
-
- if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[7],
- ee->ee_xpd[ee_mode], 1, 4, 0, TRUE))
- return (FALSE);
-
- /* Write RF values */
- for (i = 0; i < rf_size; i++) {
- AR5K_REG_WAIT(i);
- AR5K_REG_WRITE(rf5111_rf[i].rf_register, rf[i]);
- }
-
- return (TRUE);
-}
-
-/*
- * Read EEPROM Calibration data, modify RF Banks and Initialize RF5112
- */
-AR5K_BOOL
-ath5k_hw_rf5112_rfregs(struct ath_hal *hal, AR5K_CHANNEL *channel, u_int mode)
-{
- struct ath5k_eeprom_info *ee = &hal->ah_capabilities.cap_eeprom;
- u_int rf_size;
- u_int32_t *rf;
- int i, obdb = -1, bank = -1;
- u_int32_t ee_mode;
- const struct ath5k_ini_rf *rf_ini;
-
- AR5K_ASSERT_ENTRY(mode, AR5K_INI_VAL_MAX);
-
- rf = hal->ah_rf_banks;
-
- if (hal->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) {
- rf_ini = rf5112a_rf;
- rf_size = AR5K_ELEMENTS(rf5112a_rf);
- } else {
- rf_ini = rf5112_rf;
- rf_size = AR5K_ELEMENTS(rf5112_rf);
- }
-
- /* Copy values to modify them */
- for (i = 0; i < rf_size; i++) {
- if (rf_ini[i].rf_bank >=
- AR5K_RF5112_INI_RF_MAX_BANKS) {
- AR5K_PRINT("invalid bank\n");
- return (FALSE);
- }
-
- if (bank != rf_ini[i].rf_bank) {
- bank = rf_ini[i].rf_bank;
- hal->ah_offset[bank] = i;
- }
-
- rf[i] = rf_ini[i].rf_value[mode];
- }
-
- /* Modify bank 6 */
- if (channel->channel_flags & CHANNEL_2GHZ) {
- if (channel->channel_flags & CHANNEL_B)
- ee_mode = AR5K_EEPROM_MODE_11B;
- else
- ee_mode = AR5K_EEPROM_MODE_11G;
- obdb = 0;
-
- if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[6],
- ee->ee_ob[ee_mode][obdb], 3, 287, 0, TRUE))
- return (FALSE);
-
- if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[6],
- ee->ee_ob[ee_mode][obdb], 3, 290, 0, TRUE))
- return (FALSE);
- } else {
- /* For 11a, Turbo and XR */
- ee_mode = AR5K_EEPROM_MODE_11A;
- obdb = channel->freq >= 5725 ? 3 :
- (channel->freq >= 5500 ? 2 :
- (channel->freq >= 5260 ? 1 :
- (channel->freq > 4000 ? 0 : -1)));
-
- if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[6],
- ee->ee_ob[ee_mode][obdb], 3, 279, 0, TRUE))
- return (FALSE);
-
- if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[6],
- ee->ee_ob[ee_mode][obdb], 3, 282, 0, TRUE))
- return (FALSE);
- }
-
-#ifdef notyet
- ath5k_hw_rfregs_op(rf, hal->ah_offset[6],
- ee->ee_x_gain[ee_mode], 2, 270, 0, TRUE);
- ath5k_hw_rfregs_op(rf, hal->ah_offset[6],
- ee->ee_x_gain[ee_mode], 2, 257, 0, TRUE);
-#endif
-
- if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[6],
- ee->ee_xpd[ee_mode], 1, 302, 0, TRUE))
- return (FALSE);
-
- /* Modify bank 7 */
- if (!ath5k_hw_rfregs_op(rf, hal->ah_offset[7],
- ee->ee_i_gain[ee_mode], 6, 14, 0, TRUE))
- return (FALSE);
-
- /* Write RF values */
- for (i = 0; i < rf_size; i++)
- AR5K_REG_WRITE(rf_ini[i].rf_register, rf[i]);
-
- return (TRUE);
-}
-
-AR5K_BOOL
-ath5k_hw_rfgain(struct ath_hal *hal, u_int freq)
-{
- int i;
- struct ath5k_ini_rfgain *ath5k_rfg;
-
- switch (hal->ah_radio) {
- case AR5K_RF5111:
- ath5k_rfg = (struct ath5k_ini_rfgain*) &rf5111_ini_rfgain;
- break;
- case AR5K_RF5112:
- ath5k_rfg = (struct ath5k_ini_rfgain*) &rf5112_ini_rfgain;
- break;
- default:
- return (FALSE);
- }
-
- switch (freq) {
- case AR5K_INI_RFGAIN_2GHZ:
- case AR5K_INI_RFGAIN_5GHZ:
- break;
- default:
- return (FALSE);
- }
-
- for (i = 0; i < AR5K_ELEMENTS(ath5k_rfg); i++) {
- AR5K_REG_WAIT(i);
- AR5K_REG_WRITE((u_int32_t)ath5k_rfg[i].rfg_register,
- ath5k_rfg[i].rfg_value[freq]);
- }
-
- return (TRUE);
-}
-
-AR5K_RFGAIN
-ath5k_hw_get_rf_gain(struct ath_hal *hal)
-{
- u_int32_t data, type;
-
- AR5K_TRACE;
-
- if ((hal->ah_rf_banks == NULL) || (!hal->ah_gain.g_active)
- || (hal->ah_version <= AR5K_AR5211))
- return (AR5K_RFGAIN_INACTIVE);
-
- if (hal->ah_rf_gain != AR5K_RFGAIN_READ_REQUESTED)
- goto done;
-
- data = AR5K_REG_READ(AR5K_PHY_PAPD_PROBE);
-
- if (!(data & AR5K_PHY_PAPD_PROBE_TX_NEXT)) {
- hal->ah_gain.g_current =
- data >> AR5K_PHY_PAPD_PROBE_GAINF_S;
- type = AR5K_REG_MS(data, AR5K_PHY_PAPD_PROBE_TYPE);
-
- if (type == AR5K_PHY_PAPD_PROBE_TYPE_CCK)
- hal->ah_gain.g_current += AR5K_GAIN_CCK_PROBE_CORR;
-
- if (hal->ah_radio == AR5K_RF5112) {
- ath5k_hw_rfregs_gainf_corr(hal);
- hal->ah_gain.g_current =
- hal->ah_gain.g_current >= hal->ah_gain.g_f_corr
?
- (hal->ah_gain.g_current -
hal->ah_gain.g_f_corr) :
- 0;
- }
-
- if (ath5k_hw_rfregs_gain_readback(hal) &&
- AR5K_GAIN_CHECK_ADJUST(&hal->ah_gain) &&
- ath5k_hw_rfregs_gain_adjust(hal))
- hal->ah_rf_gain = AR5K_RFGAIN_NEED_CHANGE;
- }
-
- done:
- return (hal->ah_rf_gain);
-}
-
-/*
- * TX power setup
- */
-
-/*
- * Initialize the tx power table (not fully implemented)
- */
-void
-ath5k_hw_txpower_table(struct ath_hal *hal, AR5K_CHANNEL *channel, int16_t
max_power)
-{
- u_int16_t txpower, *rates;
- int i, min, max, n;
-
- rates = hal->ah_txpower.txp_rates;
-
- txpower = AR5K_TUNE_DEFAULT_TXPOWER * 2;
- if (max_power > txpower)
- txpower = max_power > AR5K_TUNE_MAX_TXPOWER ?
- AR5K_TUNE_MAX_TXPOWER : max_power;
-
- for (i = 0; i < AR5K_MAX_RATES; i++)
- rates[i] = txpower;
-
- /* XXX setup target powers by rate */
-
- hal->ah_txpower.txp_min = rates[7];
- hal->ah_txpower.txp_max = rates[0];
- hal->ah_txpower.txp_ofdm = rates[0];
-
- /* Calculate the power table */
- n = AR5K_ELEMENTS(hal->ah_txpower.txp_pcdac);
- min = AR5K_EEPROM_PCDAC_START;
- max = AR5K_EEPROM_PCDAC_STOP;
- for (i = 0; i < n; i += AR5K_EEPROM_PCDAC_STEP)
- hal->ah_txpower.txp_pcdac[i] =
-#ifdef notyet
- min + ((i * (max - min)) / n);
-#else
- min;
-#endif
-}
-
-/*
- * Set transmition power
- */
-AR5K_BOOL /*O.K. - txpower_table is unimplemented so this doesn't work*/
-ath5k_hw_txpower(struct ath_hal *hal, AR5K_CHANNEL *channel, u_int txpower)
-{
- AR5K_BOOL tpc = hal->ah_txpower.txp_tpc;
- int i;
-
- AR5K_TRACE;
- if (txpower > AR5K_TUNE_MAX_TXPOWER) {
- AR5K_PRINTF("invalid tx power: %u\n", txpower);
- return (FALSE);
- }
-
- /* Reset TX power values */
- memset(&hal->ah_txpower, 0, sizeof(hal->ah_txpower));
- hal->ah_txpower.txp_tpc = tpc;
-
- /* Initialize TX power table */
- ath5k_hw_txpower_table(hal, channel, txpower);
-
- /*
- * Write TX power values
- */
- for (i = 0; i < (AR5K_EEPROM_POWER_TABLE_SIZE / 2); i++) {
- AR5K_REG_WRITE(AR5K_PHY_PCDAC_TXPOWER(i),
- ((((hal->ah_txpower.txp_pcdac[(i << 1) + 1] << 8) | 0xff)
& 0xffff) << 16)
- | ((((hal->ah_txpower.txp_pcdac[(i << 1) ] << 8) | 0xff)
& 0xffff) )
- );
- }
-
- AR5K_REG_WRITE(AR5K_PHY_TXPOWER_RATE1,
- AR5K_TXPOWER_OFDM(3, 24) | AR5K_TXPOWER_OFDM(2, 16)
- | AR5K_TXPOWER_OFDM(1, 8) | AR5K_TXPOWER_OFDM(0, 0));
-
- AR5K_REG_WRITE(AR5K_PHY_TXPOWER_RATE2,
- AR5K_TXPOWER_OFDM(7, 24) | AR5K_TXPOWER_OFDM(6, 16)
- | AR5K_TXPOWER_OFDM(5, 8) | AR5K_TXPOWER_OFDM(4, 0));
-
- AR5K_REG_WRITE(AR5K_PHY_TXPOWER_RATE3,
- AR5K_TXPOWER_CCK(10, 24) | AR5K_TXPOWER_CCK(9, 16)
- | AR5K_TXPOWER_CCK(15, 8) | AR5K_TXPOWER_CCK(8, 0));
-
- AR5K_REG_WRITE(AR5K_PHY_TXPOWER_RATE4,
- AR5K_TXPOWER_CCK(14, 24) | AR5K_TXPOWER_CCK(13, 16)
- | AR5K_TXPOWER_CCK(12, 8) | AR5K_TXPOWER_CCK(11, 0));
-
- if (hal->ah_txpower.txp_tpc == TRUE) {
- AR5K_REG_WRITE(AR5K_PHY_TXPOWER_RATE_MAX,
- AR5K_PHY_TXPOWER_RATE_MAX_TPC_ENABLE |
- AR5K_TUNE_MAX_TXPOWER);
- } else {
- AR5K_REG_WRITE(AR5K_PHY_TXPOWER_RATE_MAX,
- AR5K_PHY_TXPOWER_RATE_MAX |
- AR5K_TUNE_MAX_TXPOWER);
- }
-
- return (TRUE);
-}
-
-AR5K_BOOL
-ath5k_hw_set_txpower_limit(struct ath_hal *hal, u_int power)
-{
- /*Just a try M.F.*/
- AR5K_CHANNEL *channel = &hal->ah_current_channel;
-
- AR5K_TRACE;
- AR5K_PRINTF("changing txpower to %d\n",power);
- return (ath5k_hw_txpower(hal, channel, power));
-}
-
-
-
-
/****************\
Misc functions
\****************/
Modified: branches/ath5k/ath5k_hw.h
===================================================================
--- branches/ath5k/ath5k_hw.h 2007-08-26 09:34:43 UTC (rev 2670)
+++ branches/ath5k/ath5k_hw.h 2007-08-26 16:17:52 UTC (rev 2671)
@@ -54,12 +54,6 @@
int32_t gos_gain;
};
-struct ath5k_gain_opt {
- u_int32_t go_default;
- u_int32_t go_steps_count;
- const struct ath5k_gain_opt_step go_step[AR5K_GAIN_STEP_COUNT];
-};
-
struct ath5k_gain {
u_int32_t g_step_idx;
u_int32_t g_current;
@@ -71,40 +65,6 @@
const struct ath5k_gain_opt_step *g_step;
};
-/*
- * Gain optimization tables...
- */
-#define AR5K_RF5111_GAIN_OPT { \
- 4, \
- 9, \
- { \
- { { 4, 1, 1, 1 }, 6 }, \
- { { 4, 0, 1, 1 }, 4 }, \
- { { 3, 1, 1, 1 }, 3 }, \
- { { 4, 0, 0, 1 }, 1 }, \
- { { 4, 1, 1, 0 }, 0 }, \
- { { 4, 0, 1, 0 }, -2 }, \
- { { 3, 1, 1, 0 }, -3 }, \
- { { 4, 0, 0, 0 }, -4 }, \
- { { 2, 1, 1, 0 }, -6 } \
- } \
-}
-
-#define AR5K_RF5112_GAIN_OPT { \
- 1, \
- 8, \
- { \
- { { 3, 0, 0, 0, 0, 0, 0 }, 6 }, \
- { { 2, 0, 0, 0, 0, 0, 0 }, 0 }, \
- { { 1, 0, 0, 0, 0, 0, 0 }, -3 }, \
- { { 0, 0, 0, 0, 0, 0, 0 }, -6 }, \
- { { 0, 1, 1, 0, 0, 0, 0 }, -8 }, \
- { { 0, 1, 1, 0, 1, 1, 0 }, -10 }, \
- { { 0, 1, 0, 1, 1, 1, 0 }, -13 }, \
- { { 0, 1, 0, 1, 1, 0, 1 }, -16 }, \
- } \
-}
-
/*
* HW SPECIFIC STRUCTS
*/
@@ -652,6 +612,9 @@
*/
/* Register dumps are done per operation mode */
+#define AR5K_INI_RFGAIN_5GHZ 0
+#define AR5K_INI_RFGAIN_2GHZ 1
+
#define AR5K_INI_VAL_11A 0
#define AR5K_INI_VAL_11A_TURBO 1
#define AR5K_INI_VAL_11B 2
@@ -663,1465 +626,17 @@
#define AR5K_RF5111_INI_RF_MAX_BANKS AR5K_MAX_RF_BANKS
#define AR5K_RF5112_INI_RF_MAX_BANKS AR5K_MAX_RF_BANKS
+static inline u_int32_t
+ath5k_hw_bitswap(u_int32_t val, u_int bits)
+{
+ u_int32_t retval = 0, bit, i;
-/* Struct to hold initial RF register values (RF Banks)*/
-struct ath5k_ini_rf {
- u_int8_t rf_bank; /* check out ath5kreg.h */
- u_int16_t rf_register; /* register address */
- u_int32_t rf_value[5]; /* register value for
- different modes (see avove) */
-};
-
-/* RF5111 mode-specific init registers */
-#define AR5K_RF5111_INI_RF {
\
- { 0, 0x989c,
\
- /* mode a/XR mode aTurbo mode b mode g mode gTurbo */
\
- { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
\
- { 0, 0x989c,
\
- { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
\
- { 0, 0x989c,
\
- { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
\
- { 0, 0x989c,
\
- { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
\
- { 0, 0x989c,
\
- { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
\
- { 0, 0x989c,
\
- { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
\
- { 0, 0x989c,
\
- { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
\
- { 0, 0x989c,
\
- { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
\
- { 0, 0x989c,
\
- { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
\
- { 0, 0x989c,
\
- { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
\
- { 0, 0x989c,
\
- { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
\
- { 0, 0x989c,
\
- { 0x00380000, 0x00380000, 0x00380000, 0x00380000, 0x00380000 } },
\
- { 0, 0x989c,
\
- { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
\
- { 0, 0x989c,
\
- { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
\
- { 0, 0x989c,
\
- { 0x00000000, 0x00000000, 0x000000c0, 0x00000080, 0x00000080 } },
\
- { 0, 0x989c,
\
- { 0x000400f9, 0x000400f9, 0x000400ff, 0x000400fd, 0x000400fd } },
\
- { 0, 0x98d4,
\
- { 0x00000000, 0x00000000, 0x00000004, 0x00000004, 0x00000004 } },
\
- { 1, 0x98d4,
\
- { 0x00000020, 0x00000020, 0x00000020, 0x00000020, 0x00000020 } },
\
- { 2, 0x98d4,
\
- { 0x00000010, 0x00000014, 0x00000010, 0x00000010, 0x00000014 } },
\
- { 3, 0x98d8,
\
- { 0x00601068, 0x00601068, 0x00601068, 0x00601068, 0x00601068 } },
\
- { 6, 0x989c,
\
- { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
\
- { 6, 0x989c,
\
- { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
\
- { 6, 0x989c,
\
- { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
\
- { 6, 0x989c,
\
- { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
\
- { 6, 0x989c,
\
- { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
\
- { 6, 0x989c,
\
- { 0x10000000, 0x10000000, 0x10000000, 0x10000000, 0x10000000 } },
\
- { 6, 0x989c,
\
- { 0x04000000, 0x04000000, 0x04000000, 0x04000000, 0x04000000 } },
\
- { 6, 0x989c,
\
- { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
\
- { 6, 0x989c,
\
- { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
\
- { 6, 0x989c,
\
- { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
\
- { 6, 0x989c,
\
- { 0x00000000, 0x00000000, 0x0a000000, 0x00000000, 0x00000000 } },
\
- { 6, 0x989c,
\
- { 0x003800c0, 0x00380080, 0x023800c0, 0x003800c0, 0x003800c0 } },
\
- { 6, 0x989c,
\
- { 0x00020006, 0x00020006, 0x00000006, 0x00020006, 0x00020006 } },
\
- { 6, 0x989c,
\
- { 0x00000089, 0x00000089, 0x00000089, 0x00000089, 0x00000089 } },
\
- { 6, 0x989c,
\
- { 0x000000a0, 0x000000a0, 0x000000a0, 0x000000a0, 0x000000a0 } },
\
- { 6, 0x989c,
\
- { 0x00040007, 0x00040007, 0x00040007, 0x00040007, 0x00040007 } },
\
- { 6, 0x98d4,
\
- { 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a } },
\
- { 7, 0x989c,
\
- { 0x00000040, 0x00000048, 0x00000040, 0x00000040, 0x00000040 } },
\
- { 7, 0x989c,
\
- { 0x00000010, 0x00000010, 0x00000010, 0x00000010, 0x00000010 } },
\
- { 7, 0x989c,
\
- { 0x00000008, 0x00000008, 0x00000008, 0x00000008, 0x00000008 } },
\
- { 7, 0x989c,
\
- { 0x0000004f, 0x0000004f, 0x0000004f, 0x0000004f, 0x0000004f } },
\
- { 7, 0x989c,
\
- { 0x000000f1, 0x000000f1, 0x00000061, 0x000000f1, 0x000000f1 } },
\
- { 7, 0x989c,
\
- { 0x0000904f, 0x0000904f, 0x0000904c, 0x0000904f, 0x0000904f } },
\
- { 7, 0x989c,
\
- { 0x0000125a, 0x0000125a, 0x0000129a, 0x0000125a, 0x0000125a } },
\
- { 7, 0x98cc,
\
- { 0x0000000e, 0x0000000e, 0x0000000f, 0x0000000e, 0x0000000e } },
\
-}
-
-/* RF5112 mode-specific init registers */
-#define AR5K_RF5112_INI_RF {
\
- { 1, 0x98d4,
\
- /* mode a/XR mode aTurbo mode b mode g mode gTurbo */
\
- { 0x00000020, 0x00000020, 0x00000020, 0x00000020, 0x00000020 } },
\
- { 2, 0x98d0,
\
- { 0x03060408, 0x03070408, 0x03060408, 0x03060408, 0x03070408 } },
\
- { 3, 0x98dc,
\
- { 0x00a0c0c0, 0x00a0c0c0, 0x00e0c0c0, 0x00e0c0c0, 0x00e0c0c0 } },
\
- { 6, 0x989c,
\
- { 0x00a00000, 0x00a00000, 0x00a00000, 0x00a00000, 0x00a00000 } },
\
- { 6, 0x989c,
\
- { 0x000a0000, 0x000a0000, 0x000a0000, 0x000a0000, 0x000a0000 } },
\
- { 6, 0x989c,
\
- { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
\
- { 6, 0x989c,
\
- { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
\
- { 6, 0x989c,
\
- { 0x00660000, 0x00660000, 0x00660000, 0x00660000, 0x00660000 } },
\
- { 6, 0x989c,
\
- { 0x00db0000, 0x00db0000, 0x00db0000, 0x00db0000, 0x00db0000 } },
\
- { 6, 0x989c,
\
- { 0x00f10000, 0x00f10000, 0x00f10000, 0x00f10000, 0x00f10000 } },
\
- { 6, 0x989c,
\
- { 0x00120000, 0x00120000, 0x00120000, 0x00120000, 0x00120000 } },
\
- { 6, 0x989c,
\
- { 0x00120000, 0x00120000, 0x00120000, 0x00120000, 0x00120000 } },
\
- { 6, 0x989c,
\
- { 0x00730000, 0x00730000, 0x00730000, 0x00730000, 0x00730000 } },
\
- { 6, 0x989c,
\
- { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
\
- { 6, 0x989c,
\
- { 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000 } },
\
- { 6, 0x989c,
\
- { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
\
- { 6, 0x989c,
\
- { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
\
- { 6, 0x989c,
\
- { 0x008b0000, 0x008b0000, 0x008b0000, 0x008b0000, 0x008b0000 } },
\
- { 6, 0x989c,
\
- { 0x00600000, 0x00600000, 0x00600000, 0x00600000, 0x00600000 } },
\
- { 6, 0x989c,
\
- { 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000 } },
\
- { 6, 0x989c,
\
- { 0x00840000, 0x00840000, 0x00840000, 0x00840000, 0x00840000 } },
\
- { 6, 0x989c,
\
- { 0x00640000, 0x00640000, 0x00640000, 0x00640000, 0x00640000 } },
\
- { 6, 0x989c,
\
- { 0x00200000, 0x00200000, 0x00200000, 0x00200000, 0x00200000 } },
\
- { 6, 0x989c,
\
- { 0x00240000, 0x00240000, 0x00240000, 0x00240000, 0x00240000 } },
\
- { 6, 0x989c,
\
- { 0x00250000, 0x00250000, 0x00250000, 0x00250000, 0x00250000 } },
\
- { 6, 0x989c,
\
- { 0x00110000, 0x00110000, 0x00110000, 0x00110000, 0x00110000 } },
\
- { 6, 0x989c,
\
- { 0x00110000, 0x00110000, 0x00110000, 0x00110000, 0x00110000 } },
\
- { 6, 0x989c,
\
- { 0x00510000, 0x00510000, 0x00510000, 0x00510000, 0x00510000 } },
\
- { 6, 0x989c,
\
- { 0x1c040000, 0x1c040000, 0x1c040000, 0x1c040000, 0x1c040000 } },
\
- { 6, 0x989c,
\
- { 0x000a0000, 0x000a0000, 0x000a0000, 0x000a0000, 0x000a0000 } },
\
- { 6, 0x989c,
\
- { 0x00a10000, 0x00a10000, 0x00a10000, 0x00a10000, 0x00a10000 } },
\
- { 6, 0x989c,
\
- { 0x00400000, 0x00400000, 0x00400000, 0x00400000, 0x00400000 } },
\
- { 6, 0x989c,
\
- { 0x03090000, 0x03090000, 0x03090000, 0x03090000, 0x03090000 } },
\
- { 6, 0x989c,
\
- { 0x06000000, 0x06000000, 0x06000000, 0x06000000, 0x06000000 } },
\
- { 6, 0x989c,
\
- { 0x000000b0, 0x000000b0, 0x000000a8, 0x000000a8, 0x000000a8 } },
\
- { 6, 0x989c,
\
- { 0x0000002e, 0x0000002e, 0x0000002e, 0x0000002e, 0x0000002e } },
\
- { 6, 0x989c,
\
- { 0x006c4a41, 0x006c4a41, 0x006c4af1, 0x006c4a61, 0x006c4a61 } },
\
- { 6, 0x989c,
\
- { 0x0050892a, 0x0050892a, 0x0050892b, 0x0050892b, 0x0050892b } },
\
- { 6, 0x989c,
\
- { 0x00842400, 0x00842400, 0x00842400, 0x00842400, 0x00842400 } },
\
- { 6, 0x989c,
\
- { 0x00c69200, 0x00c69200, 0x00c69200, 0x00c69200, 0x00c69200 } },
\
- { 6, 0x98d0,
\
- { 0x0002000c, 0x0002000c, 0x0002000c, 0x0002000c, 0x0002000c } },
\
- { 7, 0x989c,
\
- { 0x00000094, 0x00000094, 0x00000094, 0x00000094, 0x00000094 } },
\
- { 7, 0x989c,
\
- { 0x00000091, 0x00000091, 0x00000091, 0x00000091, 0x00000091 } },
\
- { 7, 0x989c,
\
- { 0x0000000a, 0x0000000a, 0x00000012, 0x00000012, 0x00000012 } },
\
- { 7, 0x989c,
\
- { 0x00000080, 0x00000080, 0x00000080, 0x00000080, 0x00000080 } },
\
- { 7, 0x989c,
\
- { 0x000000c1, 0x000000c1, 0x000000c1, 0x000000c1, 0x000000c1 } },
\
- { 7, 0x989c,
\
- { 0x00000060, 0x00000060, 0x00000060, 0x00000060, 0x00000060 } },
\
- { 7, 0x989c,
\
- { 0x000000f0, 0x000000f0, 0x000000f0, 0x000000f0, 0x000000f0 } },
\
- { 7, 0x989c,
\
- { 0x00000022, 0x00000022, 0x00000022, 0x00000022, 0x00000022 } },
\
- { 7, 0x989c,
\
- { 0x00000092, 0x00000092, 0x00000092, 0x00000092, 0x00000092 } },
\
- { 7, 0x989c,
\
- { 0x000000d4, 0x000000d4, 0x000000d4, 0x000000d4, 0x000000d4 } },
\
- { 7, 0x989c,
\
- { 0x000014cc, 0x000014cc, 0x000014cc, 0x000014cc, 0x000014cc } },
\
- { 7, 0x989c,
\
- { 0x0000048c, 0x0000048c, 0x0000048c, 0x0000048c, 0x0000048c } },
\
- { 7, 0x98c4,
\
- { 0x00000003, 0x00000003, 0x00000003, 0x00000003, 0x00000003 } },
\
+ for (i = 0; i < bits; i++) {
+ bit = (val >> i) & 1;
+ retval = (retval << 1) | bit;
}
-/* RF5112A mode-specific init registers */
-#define AR5K_RF5112A_INI_RF {
\
- { 1, 0x98d4,
\
- /* mode a/XR mode aTurbo mode b mode g mode gTurbo */
\
- { 0x00000020, 0x00000020, 0x00000020, 0x00000020, 0x00000020 } },
\
- { 2, 0x98d0,
\
- { 0x03060408, 0x03070408, 0x03060408, 0x03060408, 0x03070408 } },
\
- { 3, 0x98dc,
\
- { 0x00a0c0c0, 0x00a0c0c0, 0x00e0c0c0, 0x00e0c0c0, 0x00e0c0c0 } },
\
- { 6, 0x989c,
\
- { 0x0f000000, 0x0f000000, 0x0f000000, 0x0f000000, 0x0f000000 } },
\
- { 6, 0x989c,
\
- { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
\
- { 6, 0x989c,
\
- { 0x00800000, 0x00800000, 0x00800000, 0x00800000, 0x00800000 } },
\
- { 6, 0x989c,
\
- { 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000 } },
\
- { 6, 0x989c,
\
- { 0x00010000, 0x00010000, 0x00010000, 0x00010000, 0x00010000 } },
\
- { 6, 0x989c,
\
- { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
\
- { 6, 0x989c,
\
- { 0x00180000, 0x00180000, 0x00180000, 0x00180000, 0x00180000 } },
\
- { 6, 0x989c,
\
- { 0x00600000, 0x00600000, 0x006e0000, 0x006e0000, 0x006e0000 } },
\
- { 6, 0x989c,
\
- { 0x00c70000, 0x00c70000, 0x00c70000, 0x00c70000, 0x00c70000 } },
\
- { 6, 0x989c,
\
- { 0x004b0000, 0x004b0000, 0x004b0000, 0x004b0000, 0x004b0000 } },
\
- { 6, 0x989c,
\
- { 0x04480000, 0x04480000, 0x04480000, 0x04480000, 0x04480000 } },
\
- { 6, 0x989c,
\
- { 0x00220000, 0x00220000, 0x00220000, 0x00220000, 0x00220000 } },
\
- { 6, 0x989c,
\
- { 0x00e40000, 0x00e40000, 0x00e40000, 0x00e40000, 0x00e40000 } },
\
- { 6, 0x989c,
\
- { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
\
- { 6, 0x989c,
\
- { 0x00fc0000, 0x00fc0000, 0x00fc0000, 0x00fc0000, 0x00fc0000 } },
\
- { 6, 0x989c,
\
- { 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000, 0x00ff0000 } },
\
- { 6, 0x989c,
\
- { 0x043f0000, 0x043f0000, 0x043f0000, 0x043f0000, 0x043f0000 } },
\
- { 6, 0x989c,
\
- { 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000, 0x000c0000 } },
\
- { 6, 0x989c,
\
- { 0x00190000, 0x00190000, 0x00190000, 0x00190000, 0x00190000 } },
\
- { 6, 0x989c,
\
- { 0x00240000, 0x00240000, 0x00240000, 0x00240000, 0x00240000 } },
\
- { 6, 0x989c,
\
- { 0x00b40000, 0x00b40000, 0x00b40000, 0x00b40000, 0x00b40000 } },
\
- { 6, 0x989c,
\
- { 0x00990000, 0x00990000, 0x00990000, 0x00990000, 0x00990000 } },
\
- { 6, 0x989c,
\
- { 0x00500000, 0x00500000, 0x00500000, 0x00500000, 0x00500000 } },
\
- { 6, 0x989c,
\
- { 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000, 0x002a0000 } },
\
- { 6, 0x989c,
\
- { 0x00120000, 0x00120000, 0x00120000, 0x00120000, 0x00120000 } },
\
- { 6, 0x989c,
\
- { 0xc0320000, 0xc0320000, 0xc0320000, 0xc0320000, 0xc0320000 } },
\
- { 6, 0x989c,
\
- { 0x01740000, 0x01740000, 0x01740000, 0x01740000, 0x01740000 } },
\
- { 6, 0x989c,
\
- { 0x00110000, 0x00110000, 0x00110000, 0x00110000, 0x00110000 } },
\
- { 6, 0x989c,
\
- { 0x86280000, 0x86280000, 0x86280000, 0x86280000, 0x86280000 } },
\
- { 6, 0x989c,
\
- { 0x31840000, 0x31840000, 0x31840000, 0x31840000, 0x31840000 } },
\
- { 6, 0x989c,
\
- { 0x00020080, 0x00020080, 0x00020080, 0x00020080, 0x00020080 } },
\
- { 6, 0x989c,
\
- { 0x00080009, 0x00080009, 0x00080009, 0x00080009, 0x00080009 } },
\
- { 6, 0x989c,
\
- { 0x00000003, 0x00000003, 0x00000003, 0x00000003, 0x00000003 } },
\
- { 6, 0x989c,
\
- { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 } },
\
- { 6, 0x989c,
\
- { 0x000000b2, 0x000000b2, 0x000000b2, 0x000000b2, 0x000000b2 } },
\
- { 6, 0x989c,
\
- { 0x00b02084, 0x00b02084, 0x00b02084, 0x00b02084, 0x00b02084 } },
\
- { 6, 0x989c,
\
- { 0x004125a4, 0x004125a4, 0x004125a4, 0x004125a4, 0x004125a4 } },
\
- { 6, 0x989c,
\
- { 0x00119220, 0x00119220, 0x00119220, 0x00119220, 0x00119220 } },
\
- { 6, 0x989c,
\
- { 0x001a4800, 0x001a4800, 0x001a4800, 0x001a4800, 0x001a4800 } },
\
- { 6, 0x98d8,
\
- { 0x000b0230, 0x000b0230, 0x000b0230, 0x000b0230, 0x000b0230 } },
\
- { 7, 0x989c,
\
- { 0x00000094, 0x00000094, 0x00000094, 0x00000094, 0x00000094 } },
\
- { 7, 0x989c,
\
- { 0x00000091, 0x00000091, 0x00000091, 0x00000091, 0x00000091 } },
\
- { 7, 0x989c,
\
- { 0x00000012, 0x00000012, 0x00000012, 0x00000012, 0x00000012 } },
\
- { 7, 0x989c,
\
- { 0x00000080, 0x00000080, 0x00000080, 0x00000080, 0x00000080 } },
\
- { 7, 0x989c,
\
- { 0x000000d9, 0x000000d9, 0x000000d9, 0x000000d9, 0x000000d9 } },
\
- { 7, 0x989c,
\
- { 0x00000060, 0x00000060, 0x00000060, 0x00000060, 0x00000060 } },
\
- { 7, 0x989c,
\
- { 0x000000f0, 0x000000f0, 0x000000f0, 0x000000f0, 0x000000f0 } },
\
- { 7, 0x989c,
\
- { 0x000000a2, 0x000000a2, 0x000000a2, 0x000000a2, 0x000000a2 } },
\
- { 7, 0x989c,
\
- { 0x00000052, 0x00000052, 0x00000052, 0x00000052, 0x00000052 } },
\
- { 7, 0x989c,
\
- { 0x000000d4, 0x000000d4, 0x000000d4, 0x000000d4, 0x000000d4 } },
\
- { 7, 0x989c,
\
- { 0x000014cc, 0x000014cc, 0x000014cc, 0x000014cc, 0x000014cc } },
\
- { 7, 0x989c,
\
- { 0x0000048c, 0x0000048c, 0x0000048c, 0x0000048c, 0x0000048c } },
\
- { 7, 0x98c4,
\
- { 0x00000003, 0x00000003, 0x00000003, 0x00000003, 0x00000003 } },
\
+ return (retval);
}
-/*
- * Mode-specific RF Gain table (64bytes) for RF5111/5112
- * (RF5110 only comes with AR5210 and only supports a/turbo a
- * mode so initial RF Gain values are included in AR5K_AR5210_INI)
- */
-struct ath5k_ini_rfgain {
- u_int16_t rfg_register; /* RF Gain register address */
- u_int32_t rfg_value[2]; /* Register value [freq (see
below)] */
-#define AR5K_INI_RFGAIN_5GHZ 0
-#define AR5K_INI_RFGAIN_2GHZ 1
-};
-
-/* Initial RF Gain settings for RF5111 */
-#define AR5K_RF5111_INI_RFGAIN { \
- /* 5Ghz 2Ghz */ \
- { AR5K_RF_GAIN(0), { 0x000001a9, 0x00000000 } }, \
- { AR5K_RF_GAIN(1), { 0x000001e9, 0x00000040 } }, \
- { AR5K_RF_GAIN(2), { 0x00000029, 0x00000080 } }, \
- { AR5K_RF_GAIN(3), { 0x00000069, 0x00000150 } }, \
- { AR5K_RF_GAIN(4), { 0x00000199, 0x00000190 } }, \
- { AR5K_RF_GAIN(5), { 0x000001d9, 0x000001d0 } }, \
- { AR5K_RF_GAIN(6), { 0x00000019, 0x00000010 } }, \
- { AR5K_RF_GAIN(7), { 0x00000059, 0x00000044 } }, \
- { AR5K_RF_GAIN(8), { 0x00000099, 0x00000084 } }, \
- { AR5K_RF_GAIN(9), { 0x000001a5, 0x00000148 } }, \
- { AR5K_RF_GAIN(10), { 0x000001e5, 0x00000188 } }, \
- { AR5K_RF_GAIN(11), { 0x00000025, 0x000001c8 } }, \
- { AR5K_RF_GAIN(12), { 0x000001c8, 0x00000014 } }, \
- { AR5K_RF_GAIN(13), { 0x00000008, 0x00000042 } }, \
- { AR5K_RF_GAIN(14), { 0x00000048, 0x00000082 } }, \
- { AR5K_RF_GAIN(15), { 0x00000088, 0x00000178 } }, \
- { AR5K_RF_GAIN(16), { 0x00000198, 0x000001b8 } }, \
- { AR5K_RF_GAIN(17), { 0x000001d8, 0x000001f8 } }, \
- { AR5K_RF_GAIN(18), { 0x00000018, 0x00000012 } }, \
- { AR5K_RF_GAIN(19), { 0x00000058, 0x00000052 } }, \
- { AR5K_RF_GAIN(20), { 0x00000098, 0x00000092 } }, \
- { AR5K_RF_GAIN(21), { 0x000001a4, 0x0000017c } }, \
- { AR5K_RF_GAIN(22), { 0x000001e4, 0x000001bc } }, \
- { AR5K_RF_GAIN(23), { 0x00000024, 0x000001fc } }, \
- { AR5K_RF_GAIN(24), { 0x00000064, 0x0000000a } }, \
- { AR5K_RF_GAIN(25), { 0x000000a4, 0x0000004a } }, \
- { AR5K_RF_GAIN(26), { 0x000000e4, 0x0000008a } }, \
- { AR5K_RF_GAIN(27), { 0x0000010a, 0x0000015a } }, \
- { AR5K_RF_GAIN(28), { 0x0000014a, 0x0000019a } }, \
- { AR5K_RF_GAIN(29), { 0x0000018a, 0x000001da } }, \
- { AR5K_RF_GAIN(30), { 0x000001ca, 0x0000000e } }, \
- { AR5K_RF_GAIN(31), { 0x0000000a, 0x0000004e } }, \
- { AR5K_RF_GAIN(32), { 0x0000004a, 0x0000008e } }, \
- { AR5K_RF_GAIN(33), { 0x0000008a, 0x0000015e } }, \
- { AR5K_RF_GAIN(34), { 0x000001ba, 0x0000019e } }, \
- { AR5K_RF_GAIN(35), { 0x000001fa, 0x000001de } }, \
- { AR5K_RF_GAIN(36), { 0x0000003a, 0x00000009 } }, \
- { AR5K_RF_GAIN(37), { 0x0000007a, 0x00000049 } }, \
- { AR5K_RF_GAIN(38), { 0x00000186, 0x00000089 } }, \
- { AR5K_RF_GAIN(39), { 0x000001c6, 0x00000179 } }, \
- { AR5K_RF_GAIN(40), { 0x00000006, 0x000001b9 } }, \
- { AR5K_RF_GAIN(41), { 0x00000046, 0x000001f9 } }, \
- { AR5K_RF_GAIN(42), { 0x00000086, 0x00000039 } }, \
- { AR5K_RF_GAIN(43), { 0x000000c6, 0x00000079 } }, \
- { AR5K_RF_GAIN(44), { 0x000000c6, 0x000000b9 } }, \
- { AR5K_RF_GAIN(45), { 0x000000c6, 0x000001bd } }, \
- { AR5K_RF_GAIN(46), { 0x000000c6, 0x000001fd } }, \
- { AR5K_RF_GAIN(47), { 0x000000c6, 0x0000003d } }, \
- { AR5K_RF_GAIN(48), { 0x000000c6, 0x0000007d } }, \
- { AR5K_RF_GAIN(49), { 0x000000c6, 0x000000bd } }, \
- { AR5K_RF_GAIN(50), { 0x000000c6, 0x000000fd } }, \
- { AR5K_RF_GAIN(51), { 0x000000c6, 0x000000fd } }, \
- { AR5K_RF_GAIN(52), { 0x000000c6, 0x000000fd } }, \
- { AR5K_RF_GAIN(53), { 0x000000c6, 0x000000fd } }, \
- { AR5K_RF_GAIN(54), { 0x000000c6, 0x000000fd } }, \
- { AR5K_RF_GAIN(55), { 0x000000c6, 0x000000fd } }, \
- { AR5K_RF_GAIN(56), { 0x000000c6, 0x000000fd } }, \
- { AR5K_RF_GAIN(57), { 0x000000c6, 0x000000fd } }, \
- { AR5K_RF_GAIN(58), { 0x000000c6, 0x000000fd } }, \
- { AR5K_RF_GAIN(59), { 0x000000c6, 0x000000fd } }, \
- { AR5K_RF_GAIN(60), { 0x000000c6, 0x000000fd } }, \
- { AR5K_RF_GAIN(61), { 0x000000c6, 0x000000fd } }, \
- { AR5K_RF_GAIN(62), { 0x000000c6, 0x000000fd } }, \
- { AR5K_RF_GAIN(63), { 0x000000c6, 0x000000fd } }, \
-}
-
-/* Initial RF Gain settings for RF5112 */
-#define AR5K_RF5112_INI_RFGAIN { \
- /* 5Ghz 2Ghz */ \
- { AR5K_RF_GAIN(0), { 0x00000007, 0x00000007 } }, \
- { AR5K_RF_GAIN(1), { 0x00000047, 0x00000047 } }, \
- { AR5K_RF_GAIN(2), { 0x00000087, 0x00000087 } }, \
- { AR5K_RF_GAIN(3), { 0x000001a0, 0x000001a0 } }, \
- { AR5K_RF_GAIN(4), { 0x000001e0, 0x000001e0 } }, \
- { AR5K_RF_GAIN(5), { 0x00000020, 0x00000020 } }, \
- { AR5K_RF_GAIN(6), { 0x00000060, 0x00000060 } }, \
- { AR5K_RF_GAIN(7), { 0x000001a1, 0x000001a1 } }, \
- { AR5K_RF_GAIN(8), { 0x000001e1, 0x000001e1 } }, \
- { AR5K_RF_GAIN(9), { 0x00000021, 0x00000021 } }, \
- { AR5K_RF_GAIN(10), { 0x00000061, 0x00000061 } }, \
- { AR5K_RF_GAIN(11), { 0x00000162, 0x00000162 } }, \
- { AR5K_RF_GAIN(12), { 0x000001a2, 0x000001a2 } }, \
- { AR5K_RF_GAIN(13), { 0x000001e2, 0x000001e2 } }, \
- { AR5K_RF_GAIN(14), { 0x00000022, 0x00000022 } }, \
- { AR5K_RF_GAIN(15), { 0x00000062, 0x00000062 } }, \
- { AR5K_RF_GAIN(16), { 0x00000163, 0x00000163 } }, \
- { AR5K_RF_GAIN(17), { 0x000001a3, 0x000001a3 } }, \
- { AR5K_RF_GAIN(18), { 0x000001e3, 0x000001e3 } }, \
- { AR5K_RF_GAIN(19), { 0x00000023, 0x00000023 } }, \
- { AR5K_RF_GAIN(20), { 0x00000063, 0x00000063 } }, \
- { AR5K_RF_GAIN(21), { 0x00000184, 0x00000184 } }, \
- { AR5K_RF_GAIN(22), { 0x000001c4, 0x000001c4 } }, \
- { AR5K_RF_GAIN(23), { 0x00000004, 0x00000004 } }, \
- { AR5K_RF_GAIN(24), { 0x000001ea, 0x0000000b } }, \
- { AR5K_RF_GAIN(25), { 0x0000002a, 0x0000004b } }, \
- { AR5K_RF_GAIN(26), { 0x0000006a, 0x0000008b } }, \
- { AR5K_RF_GAIN(27), { 0x000000aa, 0x000001ac } }, \
- { AR5K_RF_GAIN(28), { 0x000001ab, 0x000001ec } }, \
- { AR5K_RF_GAIN(29), { 0x000001eb, 0x0000002c } }, \
- { AR5K_RF_GAIN(30), { 0x0000002b, 0x00000012 } }, \
- { AR5K_RF_GAIN(31), { 0x0000006b, 0x00000052 } }, \
- { AR5K_RF_GAIN(32), { 0x000000ab, 0x00000092 } }, \
- { AR5K_RF_GAIN(33), { 0x000001ac, 0x00000193 } }, \
- { AR5K_RF_GAIN(34), { 0x000001ec, 0x000001d3 } }, \
- { AR5K_RF_GAIN(35), { 0x0000002c, 0x00000013 } }, \
- { AR5K_RF_GAIN(36), { 0x0000003a, 0x00000053 } }, \
- { AR5K_RF_GAIN(37), { 0x0000007a, 0x00000093 } }, \
- { AR5K_RF_GAIN(38), { 0x000000ba, 0x00000194 } }, \
- { AR5K_RF_GAIN(39), { 0x000001bb, 0x000001d4 } }, \
- { AR5K_RF_GAIN(40), { 0x000001fb, 0x00000014 } }, \
- { AR5K_RF_GAIN(41), { 0x0000003b, 0x0000003a } }, \
- { AR5K_RF_GAIN(42), { 0x0000007b, 0x0000007a } }, \
- { AR5K_RF_GAIN(43), { 0x000000bb, 0x000000ba } }, \
- { AR5K_RF_GAIN(44), { 0x000001bc, 0x000001bb } }, \
- { AR5K_RF_GAIN(45), { 0x000001fc, 0x000001fb } }, \
- { AR5K_RF_GAIN(46), { 0x0000003c, 0x0000003b } }, \
- { AR5K_RF_GAIN(47), { 0x0000007c, 0x0000007b } }, \
- { AR5K_RF_GAIN(48), { 0x000000bc, 0x000000bb } }, \
- { AR5K_RF_GAIN(49), { 0x000000fc, 0x000001bc } }, \
- { AR5K_RF_GAIN(50), { 0x000000fc, 0x000001fc } }, \
- { AR5K_RF_GAIN(51), { 0x000000fc, 0x0000003c } }, \
- { AR5K_RF_GAIN(52), { 0x000000fc, 0x0000007c } }, \
- { AR5K_RF_GAIN(53), { 0x000000fc, 0x000000bc } }, \
- { AR5K_RF_GAIN(54), { 0x000000fc, 0x000000fc } }, \
- { AR5K_RF_GAIN(55), { 0x000000fc, 0x000000fc } }, \
- { AR5K_RF_GAIN(56), { 0x000000fc, 0x000000fc } }, \
- { AR5K_RF_GAIN(57), { 0x000000fc, 0x000000fc } }, \
- { AR5K_RF_GAIN(58), { 0x000000fc, 0x000000fc } }, \
- { AR5K_RF_GAIN(59), { 0x000000fc, 0x000000fc } }, \
- { AR5K_RF_GAIN(60), { 0x000000fc, 0x000000fc } }, \
- { AR5K_RF_GAIN(61), { 0x000000fc, 0x000000fc } }, \
- { AR5K_RF_GAIN(62), { 0x000000fc, 0x000000fc } }, \
- { AR5K_RF_GAIN(63), { 0x000000fc, 0x000000fc } }, \
-}
-
-
-
-/*
- * MAC/PHY REGISTERS
- */
-
-/*
- * Mode-independed initial register writes
- */
-
-struct ath5k_ini {
- u_int16_t ini_register;
- u_int32_t ini_value;
-
- enum {
- AR5K_INI_WRITE = 0, /* Default */
- AR5K_INI_READ = 1, /* Cleared on read */
- } ini_mode;
-};
-
-/* Initial register settings for AR5210 */
-#define AR5K_AR5210_INI { \
- /* PCU and MAC registers */ \
- { AR5K_NOQCU_TXDP0, 0 }, \
- { AR5K_NOQCU_TXDP1, 0 }, \
- { AR5K_RXDP, 0 }, \
- { AR5K_CR, 0 }, \
- { AR5K_ISR, 0, AR5K_INI_READ }, \
- { AR5K_IMR, 0 }, \
- { AR5K_IER, AR5K_IER_DISABLE }, \
- { AR5K_BSR, 0, AR5K_INI_READ }, \
- { AR5K_TXCFG, AR5K_DMASIZE_128B }, \
- { AR5K_RXCFG, AR5K_DMASIZE_128B }, \
- { AR5K_CFG, AR5K_INIT_CFG }, \
- { AR5K_TOPS, AR5K_INIT_TOPS }, \
- { AR5K_RXNOFRM, AR5K_INIT_RXNOFRM }, \
- { AR5K_RPGTO, AR5K_INIT_RPGTO }, \
- { AR5K_TXNOFRM, AR5K_INIT_TXNOFRM }, \
- { AR5K_SFR, 0 }, \
- { AR5K_MIBC, 0 }, \
- { AR5K_MISC, 0 }, \
- { AR5K_RX_FILTER_5210, 0 }, \
- { AR5K_MCAST_FILTER0_5210, 0 }, \
- { AR5K_MCAST_FILTER1_5210, 0 }, \
- { AR5K_TX_MASK0, 0 }, \
- { AR5K_TX_MASK1, 0 }, \
- { AR5K_CLR_TMASK, 0 }, \
- { AR5K_TRIG_LVL, AR5K_TUNE_MIN_TX_FIFO_THRES }, \
- { AR5K_DIAG_SW_5210, 0 }, \
- { AR5K_RSSI_THR, AR5K_TUNE_RSSI_THRES }, \
- { AR5K_TSF_L32_5210, 0 }, \
- { AR5K_TIMER0_5210, 0 }, \
- { AR5K_TIMER1_5210, 0xffffffff }, \
- { AR5K_TIMER2_5210, 0xffffffff }, \
- { AR5K_TIMER3_5210, 1 }, \
- { AR5K_CFP_DUR_5210, 0 }, \
- { AR5K_CFP_PERIOD_5210, 0 }, \
- /* PHY registers */ \
- { AR5K_PHY(0), 0x00000047 }, \
- { AR5K_PHY_AGC, 0x00000000 }, \
- { AR5K_PHY(3), 0x09848ea6 }, \
- { AR5K_PHY(4), 0x3d32e000 }, \
- { AR5K_PHY(5), 0x0000076b }, \
- { AR5K_PHY_ACT, AR5K_PHY_ACT_DISABLE }, \
- { AR5K_PHY(8), 0x02020200 }, \
- { AR5K_PHY(9), 0x00000e0e }, \
- { AR5K_PHY(10), 0x0a020201 }, \
- { AR5K_PHY(11), 0x00036ffc }, \
- { AR5K_PHY(12), 0x00000000 }, \
- { AR5K_PHY(13), 0x00000e0e }, \
- { AR5K_PHY(14), 0x00000007 }, \
- { AR5K_PHY(15), 0x00020100 }, \
- { AR5K_PHY(16), 0x89630000 }, \
- { AR5K_PHY(17), 0x1372169c }, \
- { AR5K_PHY(18), 0x0018b633 }, \
- { AR5K_PHY(19), 0x1284613c }, \
- { AR5K_PHY(20), 0x0de8b8e0 }, \
- { AR5K_PHY(21), 0x00074859 }, \
- { AR5K_PHY(22), 0x7e80beba }, \
- { AR5K_PHY(23), 0x313a665e }, \
- { AR5K_PHY_AGCCTL, 0x00001d08 },\
- { AR5K_PHY(25), 0x0001ce00 }, \
- { AR5K_PHY(26), 0x409a4190 }, \
- { AR5K_PHY(28), 0x0000000f }, \
- { AR5K_PHY(29), 0x00000080 }, \
- { AR5K_PHY(30), 0x00000004 }, \
- { AR5K_PHY(31), 0x00000018 }, /* 0x987c */ \
- { AR5K_PHY(64), 0x00000000 }, /* 0x9900 */ \
- { AR5K_PHY(65), 0x00000000 }, \
- { AR5K_PHY(66), 0x00000000 }, \
- { AR5K_PHY(67), 0x00800000 }, \
- { AR5K_PHY(68), 0x00000003 }, \
- /* BB gain table (64bytes) */ \
- { AR5K_BB_GAIN(0), 0x00000000 }, \
- { AR5K_BB_GAIN(1), 0x00000020 }, \
- { AR5K_BB_GAIN(2), 0x00000010 }, \
- { AR5K_BB_GAIN(3), 0x00000030 }, \
- { AR5K_BB_GAIN(4), 0x00000008 }, \
- { AR5K_BB_GAIN(5), 0x00000028 }, \
- { AR5K_BB_GAIN(6), 0x00000028 }, \
- { AR5K_BB_GAIN(7), 0x00000004 }, \
- { AR5K_BB_GAIN(8), 0x00000024 }, \
- { AR5K_BB_GAIN(9), 0x00000014 }, \
- { AR5K_BB_GAIN(10), 0x00000034 }, \
- { AR5K_BB_GAIN(11), 0x0000000c }, \
- { AR5K_BB_GAIN(12), 0x0000002c }, \
- { AR5K_BB_GAIN(13), 0x00000002 }, \
- { AR5K_BB_GAIN(14), 0x00000022 }, \
- { AR5K_BB_GAIN(15), 0x00000012 }, \
- { AR5K_BB_GAIN(16), 0x00000032 }, \
- { AR5K_BB_GAIN(17), 0x0000000a }, \
- { AR5K_BB_GAIN(18), 0x0000002a }, \
- { AR5K_BB_GAIN(19), 0x00000001 }, \
- { AR5K_BB_GAIN(20), 0x00000021 }, \
- { AR5K_BB_GAIN(21), 0x00000011 }, \
- { AR5K_BB_GAIN(22), 0x00000031 }, \
- { AR5K_BB_GAIN(23), 0x00000009 }, \
- { AR5K_BB_GAIN(24), 0x00000029 }, \
- { AR5K_BB_GAIN(25), 0x00000005 }, \
- { AR5K_BB_GAIN(26), 0x00000025 }, \
- { AR5K_BB_GAIN(27), 0x00000015 }, \
- { AR5K_BB_GAIN(28), 0x00000035 }, \
- { AR5K_BB_GAIN(29), 0x0000000d }, \
- { AR5K_BB_GAIN(30), 0x0000002d }, \
- { AR5K_BB_GAIN(31), 0x00000003 }, \
- { AR5K_BB_GAIN(32), 0x00000023 }, \
- { AR5K_BB_GAIN(33), 0x00000013 }, \
- { AR5K_BB_GAIN(34), 0x00000033 }, \
- { AR5K_BB_GAIN(35), 0x0000000b }, \
- { AR5K_BB_GAIN(36), 0x0000002b }, \
- { AR5K_BB_GAIN(37), 0x00000007 }, \
- { AR5K_BB_GAIN(38), 0x00000027 }, \
- { AR5K_BB_GAIN(39), 0x00000017 }, \
- { AR5K_BB_GAIN(40), 0x00000037 }, \
- { AR5K_BB_GAIN(41), 0x0000000f }, \
- { AR5K_BB_GAIN(42), 0x0000002f }, \
- { AR5K_BB_GAIN(43), 0x0000002f }, \
- { AR5K_BB_GAIN(44), 0x0000002f }, \
- { AR5K_BB_GAIN(45), 0x0000002f }, \
- { AR5K_BB_GAIN(46), 0x0000002f }, \
- { AR5K_BB_GAIN(47), 0x0000002f }, \
- { AR5K_BB_GAIN(48), 0x0000002f }, \
- { AR5K_BB_GAIN(49), 0x0000002f }, \
- { AR5K_BB_GAIN(50), 0x0000002f }, \
- { AR5K_BB_GAIN(51), 0x0000002f }, \
- { AR5K_BB_GAIN(52), 0x0000002f }, \
- { AR5K_BB_GAIN(53), 0x0000002f }, \
- { AR5K_BB_GAIN(54), 0x0000002f }, \
- { AR5K_BB_GAIN(55), 0x0000002f }, \
- { AR5K_BB_GAIN(56), 0x0000002f }, \
- { AR5K_BB_GAIN(57), 0x0000002f }, \
- { AR5K_BB_GAIN(58), 0x0000002f }, \
- { AR5K_BB_GAIN(59), 0x0000002f }, \
- { AR5K_BB_GAIN(60), 0x0000002f }, \
- { AR5K_BB_GAIN(61), 0x0000002f }, \
- { AR5K_BB_GAIN(62), 0x0000002f }, \
- { AR5K_BB_GAIN(63), 0x0000002f }, \
- /* 5110 RF gain table (64btes) */ \
- { AR5K_RF_GAIN(0), 0x0000001d }, \
- { AR5K_RF_GAIN(1), 0x0000005d }, \
- { AR5K_RF_GAIN(2), 0x0000009d }, \
- { AR5K_RF_GAIN(3), 0x000000dd }, \
- { AR5K_RF_GAIN(4), 0x0000011d }, \
- { AR5K_RF_GAIN(5), 0x00000021 }, \
- { AR5K_RF_GAIN(6), 0x00000061 }, \
- { AR5K_RF_GAIN(7), 0x000000a1 }, \
- { AR5K_RF_GAIN(8), 0x000000e1 }, \
- { AR5K_RF_GAIN(9), 0x00000031 }, \
- { AR5K_RF_GAIN(10), 0x00000071 }, \
- { AR5K_RF_GAIN(11), 0x000000b1 }, \
- { AR5K_RF_GAIN(12), 0x0000001c }, \
- { AR5K_RF_GAIN(13), 0x0000005c }, \
- { AR5K_RF_GAIN(14), 0x00000029 }, \
- { AR5K_RF_GAIN(15), 0x00000069 }, \
- { AR5K_RF_GAIN(16), 0x000000a9 }, \
- { AR5K_RF_GAIN(17), 0x00000020 }, \
- { AR5K_RF_GAIN(18), 0x00000019 }, \
- { AR5K_RF_GAIN(19), 0x00000059 }, \
- { AR5K_RF_GAIN(20), 0x00000099 }, \
- { AR5K_RF_GAIN(21), 0x00000030 }, \
- { AR5K_RF_GAIN(22), 0x00000005 }, \
- { AR5K_RF_GAIN(23), 0x00000025 }, \
- { AR5K_RF_GAIN(24), 0x00000065 }, \
- { AR5K_RF_GAIN(25), 0x000000a5 }, \
- { AR5K_RF_GAIN(26), 0x00000028 }, \
- { AR5K_RF_GAIN(27), 0x00000068 }, \
- { AR5K_RF_GAIN(28), 0x0000001f }, \
- { AR5K_RF_GAIN(29), 0x0000001e }, \
- { AR5K_RF_GAIN(30), 0x00000018 }, \
- { AR5K_RF_GAIN(31), 0x00000058 }, \
- { AR5K_RF_GAIN(32), 0x00000098 }, \
- { AR5K_RF_GAIN(33), 0x00000003 }, \
- { AR5K_RF_GAIN(34), 0x00000004 }, \
- { AR5K_RF_GAIN(35), 0x00000044 }, \
- { AR5K_RF_GAIN(36), 0x00000084 }, \
- { AR5K_RF_GAIN(37), 0x00000013 }, \
- { AR5K_RF_GAIN(38), 0x00000012 }, \
- { AR5K_RF_GAIN(39), 0x00000052 }, \
- { AR5K_RF_GAIN(40), 0x00000092 }, \
- { AR5K_RF_GAIN(41), 0x000000d2 }, \
- { AR5K_RF_GAIN(42), 0x0000002b }, \
- { AR5K_RF_GAIN(43), 0x0000002a }, \
- { AR5K_RF_GAIN(44), 0x0000006a }, \
- { AR5K_RF_GAIN(45), 0x000000aa }, \
- { AR5K_RF_GAIN(46), 0x0000001b }, \
- { AR5K_RF_GAIN(47), 0x0000001a }, \
- { AR5K_RF_GAIN(48), 0x0000005a }, \
- { AR5K_RF_GAIN(49), 0x0000009a }, \
- { AR5K_RF_GAIN(50), 0x000000da }, \
- { AR5K_RF_GAIN(51), 0x00000006 }, \
- { AR5K_RF_GAIN(52), 0x00000006 }, \
- { AR5K_RF_GAIN(53), 0x00000006 }, \
- { AR5K_RF_GAIN(54), 0x00000006 }, \
- { AR5K_RF_GAIN(55), 0x00000006 }, \
- { AR5K_RF_GAIN(56), 0x00000006 }, \
- { AR5K_RF_GAIN(57), 0x00000006 }, \
- { AR5K_RF_GAIN(58), 0x00000006 }, \
- { AR5K_RF_GAIN(59), 0x00000006 }, \
- { AR5K_RF_GAIN(60), 0x00000006 }, \
- { AR5K_RF_GAIN(61), 0x00000006 }, \
- { AR5K_RF_GAIN(62), 0x00000006 }, \
- { AR5K_RF_GAIN(63), 0x00000006 }, \
- /* PHY activation */ \
- { AR5K_PHY(53), 0x00000020 }, \
- { AR5K_PHY(51), 0x00000004 }, \
- { AR5K_PHY(50), 0x00060106 }, \
- { AR5K_PHY(39), 0x0000006d }, \
- { AR5K_PHY(48), 0x00000000 }, \
- { AR5K_PHY(52), 0x00000014 }, \
- { AR5K_PHY_ACT, AR5K_PHY_ACT_ENABLE }, \
-}
-
-
-/* Initial register settings for AR5211 */
-#define AR5K_AR5211_INI { \
- { AR5K_RXDP, 0x00000000 }, \
- { AR5K_RTSD0, 0x84849c9c }, \
- { AR5K_RTSD1, 0x7c7c7c7c }, \
- { AR5K_RXCFG, 0x00000005 }, \
- { AR5K_MIBC, 0x00000000 }, \
- { AR5K_TOPS, 0x00000008 }, \
- { AR5K_RXNOFRM, 0x00000008 }, \
- { AR5K_TXNOFRM, 0x00000010 }, \
- { AR5K_RPGTO, 0x00000000 }, \
- { AR5K_RFCNT, 0x0000001f }, \
- { AR5K_QUEUE_TXDP(0), 0x00000000 }, \
- { AR5K_QUEUE_TXDP(1), 0x00000000 }, \
- { AR5K_QUEUE_TXDP(2), 0x00000000 }, \
- { AR5K_QUEUE_TXDP(3), 0x00000000 }, \
- { AR5K_QUEUE_TXDP(4), 0x00000000 }, \
- { AR5K_QUEUE_TXDP(5), 0x00000000 }, \
- { AR5K_QUEUE_TXDP(6), 0x00000000 }, \
- { AR5K_QUEUE_TXDP(7), 0x00000000 }, \
- { AR5K_QUEUE_TXDP(8), 0x00000000 }, \
- { AR5K_QUEUE_TXDP(9), 0x00000000 }, \
- { AR5K_DCU_FP, 0x00000000 }, \
- { AR5K_STA_ID1, 0x00000000 }, \
- { AR5K_BSS_ID0, 0x00000000 }, \
- { AR5K_BSS_ID1, 0x00000000 }, \
- { AR5K_RSSI_THR, 0x00000000 }, \
- { AR5K_CFP_PERIOD_5211, 0x00000000 }, \
- { AR5K_TIMER0_5211, 0x00000030 }, \
- { AR5K_TIMER1_5211, 0x0007ffff }, \
- { AR5K_TIMER2_5211, 0x01ffffff }, \
- { AR5K_TIMER3_5211, 0x00000031 }, \
- { AR5K_CFP_DUR_5211, 0x00000000 }, \
- { AR5K_RX_FILTER_5211, 0x00000000 }, \
- { AR5K_MCAST_FILTER0_5211, 0x00000000 },\
- { AR5K_MCAST_FILTER1_5211, 0x00000002 },\
- { AR5K_DIAG_SW_5211, 0x00000000 }, \
- { AR5K_ADDAC_TEST, 0x00000000 }, \
- { AR5K_DEFAULT_ANTENNA, 0x00000000 }, \
- /* PHY registers */ \
- { AR5K_PHY_AGC, 0x00000000 }, \
- { AR5K_PHY(3), 0x2d849093 }, \
- { AR5K_PHY(4), 0x7d32e000 }, \
- { AR5K_PHY(5), 0x00000f6b }, \
- { AR5K_PHY_ACT, 0x00000000 }, \
- { AR5K_PHY(11), 0x00026ffe }, \
- { AR5K_PHY(12), 0x00000000 }, \
- { AR5K_PHY(15), 0x00020100 }, \
- { AR5K_PHY(16), 0x206a017a }, \
- { AR5K_PHY(19), 0x1284613c }, \
- { AR5K_PHY(21), 0x00000859 }, \
- { AR5K_PHY(26), 0x409a4190 }, /* 0x9868 */ \
- { AR5K_PHY(27), 0x050cb081 }, \
- { AR5K_PHY(28), 0x0000000f }, \
- { AR5K_PHY(29), 0x00000080 }, \
- { AR5K_PHY(30), 0x0000000c }, \
- { AR5K_PHY(64), 0x00000000 }, \
- { AR5K_PHY(65), 0x00000000 }, \
- { AR5K_PHY(66), 0x00000000 }, \
- { AR5K_PHY(67), 0x00800000 }, \
- { AR5K_PHY(68), 0x00000001 }, \
- { AR5K_PHY(71), 0x0000092a }, \
- { AR5K_PHY_IQ, 0x00000000 }, \
- { AR5K_PHY(73), 0x00058a05 }, \
- { AR5K_PHY(74), 0x00000001 }, \
- { AR5K_PHY(75), 0x00000000 }, \
- { AR5K_PHY_PAPD_PROBE, 0x00000000 }, \
- { AR5K_PHY(77), 0x00000000 }, /* 0x9934 */ \
- { AR5K_PHY(78), 0x00000000 }, /* 0x9938 */ \
- { AR5K_PHY(79), 0x0000003f }, /* 0x993c */ \
- { AR5K_PHY(80), 0x00000004 }, \
- { AR5K_PHY(82), 0x00000000 }, \
- { AR5K_PHY(83), 0x00000000 }, \
- { AR5K_PHY(84), 0x00000000 }, \
- { AR5K_PHY_RADAR, 0x5d50f14c }, \
- { AR5K_PHY(86), 0x00000018 }, \
- { AR5K_PHY(87), 0x004b6a8e }, \
- /* Power table (32bytes) */ \
- { AR5K_PHY_PCDAC_TXPOWER(1), 0x06ff05ff }, \
- { AR5K_PHY_PCDAC_TXPOWER(2), 0x07ff07ff }, \
- { AR5K_PHY_PCDAC_TXPOWER(3), 0x08ff08ff }, \
- { AR5K_PHY_PCDAC_TXPOWER(4), 0x09ff09ff }, \
- { AR5K_PHY_PCDAC_TXPOWER(5), 0x0aff0aff }, \
- { AR5K_PHY_PCDAC_TXPOWER(6), 0x0bff0bff }, \
- { AR5K_PHY_PCDAC_TXPOWER(7), 0x0cff0cff }, \
- { AR5K_PHY_PCDAC_TXPOWER(8), 0x0dff0dff }, \
- { AR5K_PHY_PCDAC_TXPOWER(9), 0x0fff0eff }, \
- { AR5K_PHY_PCDAC_TXPOWER(10), 0x12ff12ff }, \
- { AR5K_PHY_PCDAC_TXPOWER(11), 0x14ff13ff }, \
- { AR5K_PHY_PCDAC_TXPOWER(12), 0x16ff15ff }, \
- { AR5K_PHY_PCDAC_TXPOWER(13), 0x19ff17ff }, \
- { AR5K_PHY_PCDAC_TXPOWER(14), 0x1bff1aff }, \
- { AR5K_PHY_PCDAC_TXPOWER(15), 0x1eff1dff }, \
- { AR5K_PHY_PCDAC_TXPOWER(16), 0x23ff20ff }, \
- { AR5K_PHY_PCDAC_TXPOWER(17), 0x27ff25ff }, \
- { AR5K_PHY_PCDAC_TXPOWER(18), 0x2cff29ff }, \
- { AR5K_PHY_PCDAC_TXPOWER(19), 0x31ff2fff }, \
- { AR5K_PHY_PCDAC_TXPOWER(20), 0x37ff34ff }, \
- { AR5K_PHY_PCDAC_TXPOWER(21), 0x3aff3aff }, \
- { AR5K_PHY_PCDAC_TXPOWER(22), 0x3aff3aff }, \
- { AR5K_PHY_PCDAC_TXPOWER(23), 0x3aff3aff }, \
- { AR5K_PHY_PCDAC_TXPOWER(24), 0x3aff3aff }, \
- { AR5K_PHY_PCDAC_TXPOWER(25), 0x3aff3aff }, \
- { AR5K_PHY_PCDAC_TXPOWER(26), 0x3aff3aff }, \
- { AR5K_PHY_PCDAC_TXPOWER(27), 0x3aff3aff }, \
- { AR5K_PHY_PCDAC_TXPOWER(28), 0x3aff3aff }, \
- { AR5K_PHY_PCDAC_TXPOWER(29), 0x3aff3aff }, \
- { AR5K_PHY_PCDAC_TXPOWER(30), 0x3aff3aff }, \
- { AR5K_PHY_PCDAC_TXPOWER(31), 0x3aff3aff }, \
- { AR5K_PHY_CCKTXCTL, 0x00000000 }, \
- { AR5K_PHY(642), 0x503e4646 }, \
- { AR5K_PHY_GAIN_2GHZ, 0x6480416c }, \
- { AR5K_PHY(644), 0x0199a003 }, \
- { AR5K_PHY(645), 0x044cd610 }, \
- { AR5K_PHY(646), 0x13800040 }, \
- { AR5K_PHY(647), 0x1be00060 }, \
- { AR5K_PHY(648), 0x0c53800a }, \
- { AR5K_PHY(649), 0x0014df3b }, \
- { AR5K_PHY(650), 0x000001b5 }, \
- { AR5K_PHY(651), 0x00000020 }, \
-}
-
-/* Initial register settings for AR5212 */
-#define AR5K_AR5212_INI { \
- { AR5K_RXDP, 0x00000000 }, \
- { AR5K_RXCFG, 0x00000005 }, \
- { AR5K_MIBC, 0x00000000 }, \
- { AR5K_TOPS, 0x00000008 }, \
- { AR5K_RXNOFRM, 0x00000008 }, \
- { AR5K_TXNOFRM, 0x00000010 }, \
- { AR5K_RPGTO, 0x00000000 }, \
- { AR5K_RFCNT, 0x0000001f }, \
- { AR5K_QUEUE_TXDP(0), 0x00000000 }, \
- { AR5K_QUEUE_TXDP(1), 0x00000000 }, \
- { AR5K_QUEUE_TXDP(2), 0x00000000 }, \
- { AR5K_QUEUE_TXDP(3), 0x00000000 }, \
- { AR5K_QUEUE_TXDP(4), 0x00000000 }, \
- { AR5K_QUEUE_TXDP(5), 0x00000000 }, \
- { AR5K_QUEUE_TXDP(6), 0x00000000 }, \
- { AR5K_QUEUE_TXDP(7), 0x00000000 }, \
- { AR5K_QUEUE_TXDP(8), 0x00000000 }, \
- { AR5K_QUEUE_TXDP(9), 0x00000000 }, \
- { AR5K_DCU_FP, 0x00000000 }, \
- { AR5K_DCU_TXP, 0x00000000 }, \
- { AR5K_DCU_TX_FILTER, 0x00000000 }, \
- /* Unknown table */ \
- { 0x1078, 0x00000000 }, \
- { 0x10b8, 0x00000000 }, \
- { 0x10f8, 0x00000000 }, \
- { 0x1138, 0x00000000 }, \
- { 0x1178, 0x00000000 }, \
- { 0x11b8, 0x00000000 }, \
- { 0x11f8, 0x00000000 }, \
- { 0x1238, 0x00000000 }, \
- { 0x1278, 0x00000000 }, \
- { 0x12b8, 0x00000000 }, \
- { 0x12f8, 0x00000000 }, \
- { 0x1338, 0x00000000 }, \
- { 0x1378, 0x00000000 }, \
- { 0x13b8, 0x00000000 }, \
- { 0x13f8, 0x00000000 }, \
- { 0x1438, 0x00000000 }, \
- { 0x1478, 0x00000000 }, \
- { 0x14b8, 0x00000000 }, \
- { 0x14f8, 0x00000000 }, \
- { 0x1538, 0x00000000 }, \
- { 0x1578, 0x00000000 }, \
- { 0x15b8, 0x00000000 }, \
- { 0x15f8, 0x00000000 }, \
- { 0x1638, 0x00000000 }, \
- { 0x1678, 0x00000000 }, \
- { 0x16b8, 0x00000000 }, \
- { 0x16f8, 0x00000000 }, \
- { 0x1738, 0x00000000 }, \
- { 0x1778, 0x00000000 }, \
- { 0x17b8, 0x00000000 }, \
- { 0x17f8, 0x00000000 }, \
- { 0x103c, 0x00000000 }, \
- { 0x107c, 0x00000000 }, \
- { 0x10bc, 0x00000000 }, \
- { 0x10fc, 0x00000000 }, \
- { 0x113c, 0x00000000 }, \
- { 0x117c, 0x00000000 }, \
- { 0x11bc, 0x00000000 }, \
- { 0x11fc, 0x00000000 }, \
- { 0x123c, 0x00000000 }, \
- { 0x127c, 0x00000000 }, \
- { 0x12bc, 0x00000000 }, \
- { 0x12fc, 0x00000000 }, \
- { 0x133c, 0x00000000 }, \
- { 0x137c, 0x00000000 }, \
- { 0x13bc, 0x00000000 }, \
- { 0x13fc, 0x00000000 }, \
- { 0x143c, 0x00000000 }, \
- { 0x147c, 0x00000000 }, \
- { AR5K_STA_ID1, 0x00000000 }, \
- { AR5K_BSS_ID0, 0x00000000 }, \
- { AR5K_BSS_ID1, 0x00000000 }, \
- { AR5K_RSSI_THR, 0x00000000 }, \
- { AR5K_BEACON_5211, 0x00000000 }, \
- { AR5K_CFP_PERIOD_5211, 0x00000000 }, \
- { AR5K_TIMER0_5211, 0x00000030 }, \
- { AR5K_TIMER1_5211, 0x0007ffff }, \
- { AR5K_TIMER2_5211, 0x01ffffff }, \
- { AR5K_TIMER3_5211, 0x00000031 }, \
- { AR5K_CFP_DUR_5211, 0x00000000 }, \
- { AR5K_RX_FILTER_5211, 0x00000000 }, \
- { AR5K_DIAG_SW_5211, 0x00000000 }, \
- { AR5K_ADDAC_TEST, 0x00000000 }, \
- { AR5K_DEFAULT_ANTENNA, 0x00000000 }, \
- { 0x805c, 0xffffc7ff }, \
- { 0x8080, 0x00000000 }, \
- { AR5K_NAV_5211, 0x00000000 }, \
- { AR5K_RTS_OK_5211, 0x00000000 }, \
- { AR5K_RTS_FAIL_5211, 0x00000000 }, \
- { AR5K_ACK_FAIL_5211, 0x00000000 }, \
- { AR5K_FCS_FAIL_5211, 0x00000000 }, \
- { AR5K_BEACON_CNT_5211, 0x00000000 }, \
- { AR5K_XRMODE, 0x2a82301a }, \
- { AR5K_XRDELAY, 0x05dc01e0 }, \
- { AR5K_XRTIMEOUT, 0x1f402710 }, \
- { AR5K_XRCHIRP, 0x01f40000 }, \
- { AR5K_XRSTOMP, 0x00001e1c }, \
- { AR5K_SLEEP0, 0x0002aaaa }, \
- { AR5K_SLEEP1, 0x02005555 }, \
- { AR5K_SLEEP2, 0x00000000 }, \
- { AR5K_BSS_IDM0, 0xffffffff }, \
- { AR5K_BSS_IDM1, 0x0000ffff }, \
- { AR5K_TXPC, 0x00000000 }, \
- { AR5K_PROFCNT_TX, 0x00000000 }, \
- { AR5K_PROFCNT_RX, 0x00000000 }, \
- { AR5K_PROFCNT_RXCLR, 0x00000000 }, \
- { AR5K_PROFCNT_CYCLE, 0x00000000 }, \
- { 0x80fc, 0x00000088 }, \
- { AR5K_RATE_DUR(0), 0x00000000 }, \
- { AR5K_RATE_DUR(1), 0x0000008c }, \
- { AR5K_RATE_DUR(2), 0x000000e4 }, \
- { AR5K_RATE_DUR(3), 0x000002d5 }, \
- { AR5K_RATE_DUR(4), 0x00000000 }, \
- { AR5K_RATE_DUR(5), 0x00000000 }, \
- { AR5K_RATE_DUR(6), 0x000000a0 }, \
- { AR5K_RATE_DUR(7), 0x000001c9 }, \
- { AR5K_RATE_DUR(8), 0x0000002c }, \
- { AR5K_RATE_DUR(9), 0x0000002c }, \
- { AR5K_RATE_DUR(10), 0x00000030 }, \
- { AR5K_RATE_DUR(11), 0x0000003c }, \
- { AR5K_RATE_DUR(12), 0x0000002c }, \
- { AR5K_RATE_DUR(13), 0x0000002c }, \
- { AR5K_RATE_DUR(14), 0x00000030 }, \
- { AR5K_RATE_DUR(15), 0x0000003c }, \
- { AR5K_RATE_DUR(16), 0x00000000 }, \
- { AR5K_RATE_DUR(17), 0x00000000 }, \
- { AR5K_RATE_DUR(18), 0x00000000 }, \
- { AR5K_RATE_DUR(19), 0x00000000 }, \
- { AR5K_RATE_DUR(20), 0x00000000 }, \
- { AR5K_RATE_DUR(21), 0x00000000 }, \
- { AR5K_RATE_DUR(22), 0x00000000 }, \
- { AR5K_RATE_DUR(23), 0x00000000 }, \
- { AR5K_RATE_DUR(24), 0x000000d5 }, \
- { AR5K_RATE_DUR(25), 0x000000df }, \
- { AR5K_RATE_DUR(26), 0x00000102 }, \
- { AR5K_RATE_DUR(27), 0x0000013a }, \
- { AR5K_RATE_DUR(28), 0x00000075 }, \
- { AR5K_RATE_DUR(29), 0x0000007f }, \
- { AR5K_RATE_DUR(30), 0x000000a2 }, \
- { AR5K_RATE_DUR(31), 0x00000000 }, \
- { 0x8100, 0x00010002}, \
- { AR5K_TSF_PARM, 0x00000001 }, \
- { 0x8108, 0x000000c0 }, \
- { AR5K_PHY_ERR_FIL, 0x00000000 }, \
- { 0x8110, 0x00000168 }, \
- { 0x8114, 0x00000000 }, \
- /* Some kind of table \
- * also notice ...03<-02<-01<-00) */ \
- { 0x87c0, 0x03020100 }, \
- { 0x87c4, 0x07060504 }, \
- { 0x87c8, 0x0b0a0908 }, \
- { 0x87cc, 0x0f0e0d0c }, \
- { 0x87d0, 0x13121110 }, \
- { 0x87d4, 0x17161514 }, \
- { 0x87d8, 0x1b1a1918 }, \
- { 0x87dc, 0x1f1e1d1c }, \
- /* loop ? */ \
- { 0x87e0, 0x03020100 }, \
- { 0x87e4, 0x07060504 }, \
- { 0x87e8, 0x0b0a0908 }, \
- { 0x87ec, 0x0f0e0d0c }, \
- { 0x87f0, 0x13121110 }, \
- { 0x87f4, 0x17161514 }, \
- { 0x87f8, 0x1b1a1918 }, \
- { 0x87fc, 0x1f1e1d1c }, \
- /* PHY registers */ \
- { AR5K_PHY_AGC, 0x00000000 }, \
- { AR5K_PHY(3), 0xad848e19 }, \
- { AR5K_PHY(4), 0x7d28e000 }, \
- { AR5K_PHY_TIMING_3, 0x9c0a9f6b }, \
- { AR5K_PHY_ACT, 0x00000000 }, \
- { AR5K_PHY(11), 0x00022ffe }, \
- { AR5K_PHY(15), 0x00020100 }, \
- { AR5K_PHY(16), 0x206a017a }, \
- { AR5K_PHY(19), 0x1284613c }, \
- { AR5K_PHY(21), 0x00000859 }, \
- { AR5K_PHY(64), 0x00000000 }, \
- { AR5K_PHY(65), 0x00000000 }, \
- { AR5K_PHY(66), 0x00000000 }, \
- { AR5K_PHY(67), 0x00800000 }, \
- { AR5K_PHY(68), 0x00000001 }, \
- { AR5K_PHY(71), 0x0000092a }, \
- { AR5K_PHY_IQ, 0x05100000 }, \
- { AR5K_PHY(74), 0x00000001 }, \
- { AR5K_PHY(75), 0x00000004 }, \
- { AR5K_PHY_TXPOWER_RATE1, 0x1e1f2022 }, \
- { AR5K_PHY_TXPOWER_RATE2, 0x0a0b0c0d }, \
- { AR5K_PHY_TXPOWER_RATE_MAX, 0x0000003f },\
- { AR5K_PHY(80), 0x00000004 }, \
- { AR5K_PHY(82), 0x9280b212 }, \
- { AR5K_PHY_RADAR, 0x5d50e188 }, \
- { AR5K_PHY(86), 0x000000ff }, \
- { AR5K_PHY(87), 0x004b6a8e }, \
- { AR5K_PHY(90), 0x000003ce }, \
- { AR5K_PHY(92), 0x192fb515 }, \
- { AR5K_PHY(93), 0x00000000 }, \
- { AR5K_PHY(94), 0x00000001 }, \
- { AR5K_PHY(95), 0x00000000 }, \
- /* Power table (32bytes) */ \
- { AR5K_PHY_PCDAC_TXPOWER(1), 0x10ff10ff }, \
- { AR5K_PHY_PCDAC_TXPOWER(2), 0x10ff10ff }, \
- { AR5K_PHY_PCDAC_TXPOWER(3), 0x10ff10ff }, \
- { AR5K_PHY_PCDAC_TXPOWER(4), 0x10ff10ff }, \
- { AR5K_PHY_PCDAC_TXPOWER(5), 0x10ff10ff }, \
- { AR5K_PHY_PCDAC_TXPOWER(6), 0x10ff10ff }, \
- { AR5K_PHY_PCDAC_TXPOWER(7), 0x10ff10ff }, \
- { AR5K_PHY_PCDAC_TXPOWER(8), 0x10ff10ff }, \
- { AR5K_PHY_PCDAC_TXPOWER(9), 0x10ff10ff }, \
- { AR5K_PHY_PCDAC_TXPOWER(10), 0x10ff10ff }, \
- { AR5K_PHY_PCDAC_TXPOWER(11), 0x10ff10ff }, \
- { AR5K_PHY_PCDAC_TXPOWER(12), 0x10ff10ff }, \
- { AR5K_PHY_PCDAC_TXPOWER(13), 0x10ff10ff }, \
- { AR5K_PHY_PCDAC_TXPOWER(14), 0x10ff10ff }, \
- { AR5K_PHY_PCDAC_TXPOWER(15), 0x10ff10ff }, \
- { AR5K_PHY_PCDAC_TXPOWER(16), 0x10ff10ff }, \
- { AR5K_PHY_PCDAC_TXPOWER(17), 0x10ff10ff }, \
- { AR5K_PHY_PCDAC_TXPOWER(18), 0x10ff10ff }, \
- { AR5K_PHY_PCDAC_TXPOWER(19), 0x10ff10ff }, \
- { AR5K_PHY_PCDAC_TXPOWER(20), 0x10ff10ff }, \
- { AR5K_PHY_PCDAC_TXPOWER(21), 0x10ff10ff }, \
- { AR5K_PHY_PCDAC_TXPOWER(22), 0x10ff10ff }, \
- { AR5K_PHY_PCDAC_TXPOWER(23), 0x10ff10ff }, \
- { AR5K_PHY_PCDAC_TXPOWER(24), 0x10ff10ff }, \
- { AR5K_PHY_PCDAC_TXPOWER(25), 0x10ff10ff }, \
- { AR5K_PHY_PCDAC_TXPOWER(26), 0x10ff10ff }, \
- { AR5K_PHY_PCDAC_TXPOWER(27), 0x10ff10ff }, \
- { AR5K_PHY_PCDAC_TXPOWER(28), 0x10ff10ff }, \
- { AR5K_PHY_PCDAC_TXPOWER(29), 0x10ff10ff }, \
- { AR5K_PHY_PCDAC_TXPOWER(30), 0x10ff10ff }, \
- { AR5K_PHY_PCDAC_TXPOWER(31),0x10ff10ff }, \
- { AR5K_PHY(644), 0x0080a333 }, \
- { AR5K_PHY(645), 0x00206c10 }, \
- { AR5K_PHY(646), 0x009c4060 }, \
- { AR5K_PHY(647), 0x1483800a }, \
- { AR5K_PHY(648), 0x01831061 }, \
- { AR5K_PHY(649), 0x00000400 }, \
- { AR5K_PHY(650), 0x000001b5 }, \
- { AR5K_PHY(651), 0x00000000 }, \
- { AR5K_PHY_TXPOWER_RATE3, 0x20202020 }, \
- { AR5K_PHY_TXPOWER_RATE2, 0x20202020 }, \
- { AR5K_PHY(655), 0x13c889af }, \
- { AR5K_PHY(656), 0x38490a20 }, \
- { AR5K_PHY(657), 0x00007bb6 }, \
- { AR5K_PHY(658), 0x0fff3ffc }, \
- { AR5K_PHY_CCKTXCTL, 0x00000000 }, \
-}
-
-/*
- * Initial BaseBand Gain settings for RF5111/5112
- * (only AR5210 comes with RF5110 so initial
- * BB Gain settings are included in AR5K_AR5210_INI)
- */
-
-/* RF5111 Initial BaseBand Gain settings */
-# |
