Re: CPLD in circuit programming

----- Original Message -----
From: "V Efremov" <vefremov-Wuw85uim5zDR7s880joybQ@xxxxxxxxxxxxxxxx>
To: <tini-6tN4nzCoH/hBDgjK7y7TUQ@xxxxxxxxxxxxxxxx>
Sent: Thursday, June 12, 2003 9:43 AM
Subject: [TINI] CPLD in circuit programming


> Hi list,
>
> Has anyone tried programming the xilinx CPLD from the TINIIn400 itself?
> There is an appnote an some source code how to do so from a generic 8051,
> but I wonder what the implications on the bus may be.
>
> Is the XILINX in disconnected (high impedance) state while the programming
> is in progress?
>

This is a very valid question. For Lattice parts, specifically M4A3 and M4A5
series, the pins are tri-stated during the programming process as the
devices are first erased by the programming sequence. The pins become
'active' at the end of the programming cycle. It is important to design your
logic and choose appropriate logic senses so that this does not cause a
problem (also the first time the board is powered the pins will be
tri-stated because the PLD is blank). If, for example, the PLD decodes a
buffer to enable data onto the TINI data bus during a register read, you
should choose an active low enable for this buffer and put external pull-up
on the enable so that it is off during the programming cycle.

Mark.

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