Subject: Re: gmake: how to avoid $$@ usage? - msg#00002

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Re: gmake: how to avoid $$@ usage?

"Paul D. Smith" <psmith@xxxxxxx> wrote in news:vpdrzmxnbihf.fsf@xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx: > Without seeing a REAL example of what you're trying to do it's > difficult to determine how much power you need. True, true. And I have to support a version of make that doesn't feature the $(eval) function (Rational's clearmake in GNU compat mode), unfortunately. I can't even use the $(if) function. Nor $(call). Ok, here's a totally different example to show exactly what I need to support (sorry, this is a bit long/detailed). Effectively the same problem, though (prereq's generated based on target name). The user will specify programs (exe's) to create in an agreed-upon variable name called PROGRAMS. e.g., PROGRAMS = foo.exe bar.exe ............. Now, the object files (prereqs) that make up (are linked to) each executable in that list is determined with the following logic, in this order (will stop at the first that works): 1. check for a variable called <targname>_OFILES. If it exists, use the objects listed therein. If not, try #2... 2. check for a variable called OFILES. If it exists, use its contents. If not, use #3. 3. assume there is only one object file that is needed, and its name will be <targname_prefix>.obj (or .o on Unix). i.e., in the above example, foo.o is the prereq for foo.exe, and bar.o for bar.exe. So, if the user sets: foo.exe_OFILES = a.obj b.obj c.obj Then the generated targ/prereq line for foo.exe would need to be: foo.exe : a.obj b.obj c.obj [commands] The template that I write to generate the above is of the form: ${PROGRAMS} : ${_OFILES_} [commands] _OFILES_ = <logic here to generate correct object prereqs> Any idea on a clean way to approach this? I'd rather not have to generate makefiles on the fly to do it, but if that's the only way (without $(eval), $(if), etc.), I can look into that. Thanks, Ernest

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Re: gmake: how to avoid $$@ usage?

Ernest wrote: True, true. And I have to support a version of make that doesn't feature the $(eval) function (Rational's clearmake in GNU compat mode), unfortunately. I can't even use the $(if) function. Nor $(call). Yuck! Why do you have to use ClearMake? John. -- John Graham-Cumming jgc@xxxxxxx Home: http://www.jgc.org/ Work: http://www.electric-cloud.com/ POPFile: http://getpopfile.org/ GNU Make Standard Library: http://gmsl.sf.net/

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Re: gmake: how to avoid $$@ usage?

"Paul D. Smith" <psmith@xxxxxxx> wrote in news:vpdrzmxnbihf.fsf@xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx: > Without seeing a REAL example of what you're trying to do it's > difficult to determine how much power you need. True, true. And I have to support a version of make that doesn't feature the $(eval) function (Rational's clearmake in GNU compat mode), unfortunately. I can't even use the $(if) function. Nor $(call). Ok, here's a totally different example to show exactly what I need to support (sorry, this is a bit long/detailed). Effectively the same problem, though (prereq's generated based on target name). The user will specify programs (exe's) to create in an agreed-upon variable name called PROGRAMS. e.g., PROGRAMS = foo.exe bar.exe ............. Now, the object files (prereqs) that make up (are linked to) each executable in that list is determined with the following logic, in this order (will stop at the first that works): 1. check for a variable called <targname>_OFILES. If it exists, use the objects listed therein. If not, try #2... 2. check for a variable called OFILES. If it exists, use its contents. If not, use #3. 3. assume there is only one object file that is needed, and its name will be <targname_prefix>.obj (or .o on Unix). i.e., in the above example, foo.o is the prereq for foo.exe, and bar.o for bar.exe. So, if the user sets: foo.exe_OFILES = a.obj b.obj c.obj Then the generated targ/prereq line for foo.exe would need to be: foo.exe : a.obj b.obj c.obj [commands] The template that I write to generate the above is of the form: ${PROGRAMS} : ${_OFILES_} [commands] _OFILES_ = <logic here to generate correct object prereqs> Any idea on a clean way to approach this? I'd rather not have to generate makefiles on the fly to do it, but if that's the only way (without $(eval), $(if), etc.), I can look into that. Thanks, Ernest

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Re: gmake: how to avoid $$@ usage?

"Paul D. Smith" <psmith@xxxxxxx> wrote in news:vpdrsm3fxghd.fsf@xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx: > If you're restricted to the capabilities of clearmake -C gnu, then you > have no chance. You'll have to generate makefiles. And, clearmake > doesn't support GNU make's auto-re-exec method so you'll have to > actually do this by invoking clearmake twice, explicitly. Actually, I think I found a way today to do this with $(shell) so I don't have to re-invoke make (which wouldn't work since the sub-make wouldn't have all the currently defined vars, and there are a LOT of them). For example: ################################################ # kludge to mimic an $(if)-like conditional for var defintion _defined_ = $(subst 000,${${IF}},$(subst 010,${${ELSE}},0$(words $(findstring undefined,$(origin ${VAR})))0)) # this doesn't include case #3, but that's academic to add _OFILES_ = $(foreach VAR,${prog}_OFILES,$(foreach IF,${prog}_OFILES, $(foreach ELSE,OFILES,${_defined_}))) # now create makefile2 at parse time dummy := $(foreach prog,${PROGRAMS},$(shell echo ${prog} : ${_OFILES_} >> makefile2)) # include it, so it's as if we have the targ:prereq lists explict include makefile2 ${PROGRAMS} : # prereq's have already been set in makefile2 # commands here ################################################ So makefile2 will contain simple targ:prereq lines (no commands) for all words listed in PROGRAMS. e.g., foo.exe : a.obj b.obj c.obj bar.exe : d.obj e.obj Necessity is the mother of invention, right? 8^) Whew! Cheers, Ernest