I am trying different OR0 register settings to try to
mess with the timing. I found out that the CPU always
ends on the same instruction and then reads the first
four bytes of the flash (0x27, 0x05, 0x19, 0x56),
which are the first four bytes of u-boot.bin, and then
stops. Here is the actual C and assembly code that it
fails on:
150:cpu_init.c **** defined(CONFIG_RAPTOR) || \
151:cpu_init.c **** (defined(CONFIG_MPC860T) &&
defined(CONFIG_FADS))
152:cpu_init.c ****
153:cpu_init.c **** memctl->memc_br0 =
CFG_BR0_PRELIM;
330 .LM19:
331 0058 3C00FFF0 lis 0,0xfff0
333 .LM20:
334 005c 556B052A rlwinm 11,11,0,20,21
336 .LM21:
337 0060 616B0001 ori 11,11,1
339 .LM22:
340 0064 91630100 stw 11,256(3)
342 .LM23:
343 0068 60000401 ori 0,0,1025
154:cpu_init.c **** #endif
155:cpu_init.c ****
156:cpu_init.c **** #if defined(CFG_OR0_REMAP)
157:cpu_init.c **** memctl->memc_or0 =
CFG_OR0_REMAP;
345 .LM24:
346 006c 3D40FFF8 lis 10,0xfff8
348 .LM25:
349 0070 90030100 stw 0,256(3)
351 .LM26:
352 0074 39230100 addi 9,3,256
354 .LM27:
355 0078 614A0FF6 ori 10,10,4086
356 007c 91490004 stw 10,4(9)
166:cpu_init.c **** /* now restrict to
preliminary range */
167:cpu_init.c **** memctl->memc_br0 =
CFG_BR0_PRELIM;
358 .LM28:
359 0080 90030100 stw 0,256(3)
168:cpu_init.c **** memctl->memc_or0 =
CFG_OR0_PRELIM;
361 .LM29:
362 0084 91490004 stw 10,4(9)
Instruction 0074 at line 352 is always the last
instruction that it runs before reading the first four
bytes from the flash. So it looks like the problem
occurs as soon as it tries to write to OR0.
Thanks again for everyones help!
__________________________________
Do you Yahoo!?
New Yahoo! Photos - easier uploading and sharing.
http://photos.yahoo.com/
-------------------------------------------------------
This SF.net email is sponsored by: IBM Linux Tutorials.
Become an expert in LINUX or just sharpen your skills. Sign up for IBM's
Free Linux Tutorials. Learn everything from the bash shell to sys admin.
Click now! http://ads.osdn.com/?ad_id=1278&alloc_id=3371&op=click
|
